Method for depositing interconnection metallurgy using low tempe

Details Method for depositing interconnection metallurgy using low tempe Method for depositing interconnection metallurgy using low tempe

1991-02-13

1992-09-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437196, 148DIG130, H01L 2128

Patent

active

051438674

ABSTRACT:
A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400.degree. C. A low melting point alloy of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy. In a third embodiment, the deposited alloy is planarized and then a sink layer is deposited onto the planarized interconnection structure. The structure is annealed in order to allow the alloying element to diffuse into the sink layer. The sink layer is then removed by chemical mechanical polishing.

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Marks, R. F., et al. "Thermally Conductive Bonding of Silicon Chip Employing Metal Multilayer", IBM Technical Disclosure Bulletin, 27 (10A):5882 (1985).

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