Method for depositing a flow fill layer on an integrated circuit

Details Method for depositing a flow fill layer on an integrated circuit Method for depositing a flow fill layer on an integrated circuit

1996-12-19

1997-11-25

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437235, 437238, A01L 21316

Patent

active

056912471

ABSTRACT:
An improved method for depositing the cap layer of a flow fill layer of an integrated circuit. The cap layer is deposited in at least two steps, instead of all at once.

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Kiermasz, A. Et al, "Planarisation for Sub-Micron Devices Utilising a New Chemistry", DUMIC Conference, pp. 94-100, Feb. 1995.
Matsuura, M. Et al, "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications", IEEE IEDM, 1994, pp. 117-120.
Dobson, C.D. et al, "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 ", Semiconductor Int'l., pp. 85-88, Dec. 1994.
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McClatchie, S. Et al, "Inorganic CVD Planarization", European Semiconductor, pp. 21-22, Sep. 1995.
Electotech Corp., brochure regarding Advanced Planarization Process.

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