Method for depinning the fermi level of a semiconductor at...

Semiconductor device manufacturing: process – Forming schottky junction – Combined with formation of ohmic contact to semiconductor...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S775000, C438S778000, C257SE21192, C257SE21302

Reexamination Certificate

active

07884003

ABSTRACT:
An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm2or even less than or equal to 1 Ω-μm2for the electrical device.

REFERENCES:
patent: 3590471 (1971-07-01), Lepselter et al.
patent: 3708360 (1973-01-01), Wakefield, Jr. et al.
patent: 3983264 (1976-09-01), Schroen et al.
patent: 4056642 (1977-11-01), Saxena et al.
patent: 4300152 (1981-11-01), Lepselter
patent: 4485550 (1984-12-01), Koeneke et al.
patent: 5021365 (1991-06-01), Kirchner et al.
patent: 5399206 (1995-03-01), de Lyon
patent: 5578848 (1996-11-01), Kwong et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5612567 (1997-03-01), Baliga
patent: 5663584 (1997-09-01), Welch
patent: 5801398 (1998-09-01), Hebiguchi
patent: 5801444 (1998-09-01), Aboelfotoh et al.
patent: 5888891 (1999-03-01), Gould
patent: 5939763 (1999-08-01), Hao et al.
patent: 6037605 (2000-03-01), Yoshimura
patent: 6096590 (2000-08-01), Chan et al.
patent: 6150286 (2000-11-01), Sun et al.
patent: 6198113 (2001-03-01), Grupp
patent: 6207976 (2001-03-01), Takshashi et al.
patent: 6261932 (2001-07-01), Hulfachor
patent: 6291866 (2001-09-01), Wallace et al.
patent: 6291867 (2001-09-01), Wallace et al.
patent: 6303479 (2001-10-01), Snyder
patent: 7084423 (2006-08-01), Grupp et al.
patent: 7176483 (2007-02-01), Grupp et al.
patent: 2003/0121468 (2003-07-01), Boone et al.
patent: 2004/0026687 (2004-02-01), Grupp et al.
patent: 2005/0093027 (2005-05-01), Grupp et al.
patent: 0295490 (1988-12-01), None
Wang, Lie , et al., “High Barrier GaN Schottky Diodes: Pt/GaN and Pd/GaN”, Dept. of Electrical Eng., Univ. of Minnesota, Minneapolis, Minnesota 55455; Appl. Phys. Letters, vol. 68(9), (Feb. 26, 1996),pp. 1267-1270.
Widjaja, Yuniarto , et al., “Ab Initio Study and Decomposition of NH3 on Si(100)-(2×1)”, J. Phy. Chem B, (2000), pp. 2527-2533.
Wright, Peter J., et al., “Hot-Electron Immunity of SiO2 Dielectrics with Fluorine Incorporation”, IEEE Electron Device Letters, vol. 10, No. 8, (Aug. 8, 1989),pp. 347-348.
Y. Hayafuji, et al., “Nitridation of Silicon and Oxidized-Silicon”, Sony Corp. Research Center, 174 Fujitsuka-Cho, Hodogaya-Ku, Yokohama, 240 Japan; J. Electrochem. Soc.: Solid State Science and Techology, (Sep. 1982).
Y. K. Kim, et al., “Metal-Dependent Fermi-Level Movement in the Metal/Sulfur-Passivated InGaP Contact”, J. Vac Sci. Technology A 15(3), (1997),pp. 1124-1128.
Yang, Hanyang , et al., “The Effects of Interfacial Sub-Oxide Transition Regions and Monolayer Level Nitridation on Tunneling Currents in Silicon Devices”, IEEE Electron Device Letters, vol. 21, No. 2, (Feb. 2, 2000),pp. 76-78.
Blosse, A., et al., “A Novel Low Cost 65nm CMOS Process Architecture With Self Aligned Isolation and W Cladded Source/Drain”, IEEE, Transactions of 2004 International Electron Device Meeting, pp. 669-672.
Connelly, Daniel, et al., “Optimizing Schottky S/D Offset for 25-nm Dual-Gate CMOS Performance”, IEEE Trans. Electron Devices, vol. 47 No. 5, (2003), pp. 1028-1034.
Edelstein, D., et al., “Full Copper Wiring in a Sub-0.25 mm CMOS ULSI Technology”, Proceedings of the IEEE International Electron Device Meeting, (Dec. 1997), pp. 773-776.
Gopalakrishnan, Kailash, et al., “Impact Ionization MOS (I-MOS)-Part I: Device and Circuit Simulations”, IEEE Transactions Electron Devices, vol. 52, No. 1, (2005), pp. 69-76.
Kedzierski, Jakub, et al., “Extension and Source/Drain Design for High-Performance FinFET Devices”, IEEE Trans. Electron Devices, vol. 50, No. 4, (Apr. 2003), pp. 952-958.
Thompson, Scott E., et al., “A Logic Nanotechnology Featuring Strained-Silicon”, IEEE Electron Device Letters, vol. 25, No. 4, (2004), pp. 191-193.
Wei, C.S., et al., “The Use of Selective Electroless Metal Deposition for Micron Size Contact Fill”, IEEE International Electron Device Meeting Technical Digest, (1988), pp. 446-449.
Yagishita, Atsushi, et al., “High Performance Damascene Metal Gate MOSFET's for 0.1 mm Regime”, IEEE Trans. Electron Devices, vol. 47, No. 5, (2000), pp. 1028-1034.
Aberle, Armin G., et al., “Injection-Level Dependent Surface Recombination Velocities at the Silicon-Plasma Silicon Nitrite Interface”, Institut fur Solaernergieforschung, ISFH, D-3 1860 Emmerthal, Germany, (Mar. 9, 1995),pp. 2828-2830.
B. J. Zhang, et al., “Schottky Diodes of Ni/Au on n-GaN Grown on Sapphire and SiC Substrates”, Applied Physics Letters, vol. 79, No. 16, (Oct. 15, 2001),pp. 2567-2569.
B.R. Weinberger, et al., “Surface Chemistry of HF Passivation Silicon: X-Ray Photoelectron and Lon Scattering Spectroscopy Results”, J. Appl. Phys. 60(9), (11/186),pp. 3232-3234.
C.L. Chen, et al., “High Quality Native-Oxide-Free Ultrathin Oxide Grown by In-Situ HF-Vapor Treatment”, Electronic Letters, vol. 36, No. 11, (May 25, 2000),pp. 981-983.
Chung-Kuang, Huang, et al., “Two-Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nn”, IEEE, pp. 842-848.
D. J. Chadi, et al., “Fermi-Level-Pinning Defects in Highly n-Doped Silicon”, Physical Review Letters, vol. 79, No. 24, NEC Research Institute, Princeton New Jersey 08540-6634, (Dec. 1997),pp. 4834-4837.
E. Yablonovitch, et al., “Unusually Low Surface-Recombination Velocity on Silicon and Germanium Surfaces”, Physical Review Letters, vol. 57, No. 2, (Jul. 14, 1986),pp. 249-252.
F. A. Padovani, “Forward Voltage-Current Characteristics of Metal-Silicon Schottky Barriers”, Texas Instruments, Inc., Dallas Texas, (Sep. 15, 1966),pp. 892-892.
G.B. Akers, et al., “Effects of Thermal Stability and Roughness on Electrical Properties of Tantalus Oxide Gates”, Mat. Res., Soc. Symp. Proc., vol. 567, Materials Research Society, (1999),pp. 391-395.
Hasegawa, Hideki , et al., “Upinning of Fermi Level in Nanometer-Sized Schottky Contacts on GaAs and InP”, Reseach Center for Interface Quantum Electronics and Graduate School of Electronics and Info. Eng, Hokkaido Univ, Japan, (2000),pp. 92-96.
Heine, Volker , “Theory of Surface States”, Physical Review Letters, vol. 138, No. 6A, Tell Telephone Lab., Murphy Jill, New Jersey, (Jun. 4, 1965).
Huang, Feng-Jung , “Metal-Oxide Semiconductor Field-Effect Transistors Using Schottky Barrier Drains”, Electronics Letters, vol. 33, No. 15, (Jul. 17, 1997),pp. 1341-1342.
I. Shalish, et al., “Yellow Luminescence and Fermi Level Pinning in GaN Layers”, American Institute of Physics, vol. 77, No. 7, (Aug. 14, 2000),pp. 987-989.
Internet, http://www.rciqe.hokudai.ac.jp/RCIQEold/ResearchAchievements.html, downloaded (Apr. 12, 2002).
Izumi, Hirot , et al., “43 Hydrogen Termination: The Ideally Finished Silicon Surface”, Ultraclean Surface Processing of Silicon Wafers: Secrets of Vlsi Manufacturing http://halloftechnology.com/electrical—optical/986.shtml, (Nov. 1998).
J. Hilsenbeck, et al., “Aging Behavior of AlGaN/GaN HFETs With Advanced Ohmic and Schottky Contacts”, Electronic letters, vol. 36, No. 11, (May 25, 2000),pp. 980-981.
J. Tersoff, “Schottky Barrier Heightsand the Continuum of Gap States”, Physical Review Letters, vol. 52, No. 6, AT&T Bell Lab., Murphy Jill, New Jersey 07974, (Feb. 6, 1984)

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for depinning the fermi level of a semiconductor at... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for depinning the fermi level of a semiconductor at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for depinning the fermi level of a semiconductor at... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2649894

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.