Coded data generation or conversion – Code generator or transmitter
Reexamination Certificate
2003-06-16
2004-08-10
Young, Brian (Department: 2819)
Coded data generation or conversion
Code generator or transmitter
C327S310000
Reexamination Certificate
active
06774836
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to design and operation of high-frequency clocked digital circuit systems, and in particular to method and system for reducing delta I-noise in said digital circuit system.
The operation speed of today's computer systems approach sub-nanosecond cycle times. The average switching activity and therefore the average power supply current I demand can fluctuate, i.e., change within few nanoseconds. E.g., delta-I=140A current fluctuation of the average power supply current is typical for the multiprocessor multi-chip module of the prior art IBM zSeries 900 system. The fluctuation of the average current demand can be periodic or non-periodic. Due to the parasitic inductance along the power distribution path from the power supply to the individual chips the on-chip power supply voltage deviates temporarily from its nominal level in reaction of a switching activity change. The expression “fluctuation” is used in here for denoting the rise or drop of a physical quantity, such as current I or supply voltage U, whereas the term “change” will be primarily used for denoting a status transition associated with a given activity unit on the chip, e.g., from “switching” to “quiet”. These power supply voltage deviations are called high- and mid-frequency delta-I noise.
In order to reduce the power supply delta-I noise, decoupling capacitors are placed in prior art along the power supply path, on chips, modules, cards and boards. These decoupling capacitors can sink and source extra current and thus reduce the impact of delta-I on the power supply voltage. However, the decoupling capacitors and all parasitic partial inductance of the power supply path also create resonance loops having various resonance frequencies, which may increase the delta-I noise, if a resonance frequency and the frequency of a periodic switching change coincide. This prior art is described in H. B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI”, Addison-Wesley Publishing Company, 1990, pp. 303-325, or in W. D. Becker, et al, “Modeling, Simulation and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systems”,
IEEE Trans. Compon., Packaging, and Manuf. Technol., Part B: Advanced Packaging
, vol. 21, no. 2, pp. 157-163, May 1998, or in D. Herrell, B. Beker, “Power system design for high performance PC microprocessors”, IEEE International Workshop on Chip-Package Codesign CPD'98, pp. 46-47, 1998.
Delta-I noise is one contribution to the overall power supply noise budget and can jeopardize system function and reliability.
FIG. 1
is intended to illustrate the general problem. It shows the on-chip power supply noise voltage after starting operation, i.e., switching with 1 nanosecond (ns) cycle time, and 140A average power supply current, which represents a delta-I current step from 0 A to 140 A. The power supply voltage behavior has been obtained by simulation and confirmed by measurements, see B. Garben, M. F. McAllister, “Novel Methodology for Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards and Verification by Measurements”, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 69-72, 2000. High frequency noise (1 ns period) and mid frequency noise (132 ns period) are superimposed. The actual on-chip power supply voltage behaves the same around the nominal voltage level (e.g. 1.2V).
The damped mid-frequency oscillation with initially 57 mV peak on-chip power supply voltage noise is caused by the resonant loop consisting of all on-module capacitors, i.e., on-module power supply decoupling capacitors plus capacitance of all chips, all board decoupling capacitors and the effective power supply path loop inductance between the two sets of capacitors.
With reference to Plot a) of
FIG. 2
the on-chip power supply noise voltage of the same packaging arrangement is shown, but now, switching and non-switching depicted as “quiet”-time slots repeat every 66 ns. The delta-I repetition rate coincides with the package resonance of 132 ns. The peak on-chip power supply delta-I noise equals 74 mV during the 1st quiet time slot and increases to 103 mV during the 2nd quiet time slot. Both peak noise values exceed the 57 mV, seen during a single switching activity change. The peak mid-frequency on-chip power supply delta-I noise during periodic activity changes saturates at approx. 135 mV beyond 8 periods.
The saturated peak on-chip mid-frequency delta-I noise increases with increasing conductivity within the resonance loop. E.g. if the overall conductivity within the loop is doubled, the maximum on-chip noise reaches 202 mV after 10 periodic switching activity changes without any saturation tendency (
FIG. 2
, curve b). This example demonstrates how the peak on-chip power supply voltage noise of periodic/repeated activity changes can significantly exceed the peak values of a single activity change.
In prior art, high performance computer systems such as the IBM zSeries 900 apply the following technical features in order to damp the delta I-noise:
1. many decoupling capacitors on chips, on the Multi-Chip-Module (MCM) and on the board close to the MCM,
2. sandwiching of VDD and GND planes closely to each other, in cards and boards to provide a low effective power supply loop inductance.
However, these design efforts also reduce the effective resistance of the resonant loop and therefore increase the power supply delta-I noise sensitivity in case of a resonance condition.
Delta-I noise and its increase due to resonant effects is considered in the system noise budget and in signal timing calculations. The following two theoretical approaches are considered today to account for large non-periodic switching activity changes, whereas periodic activity changes are not regarded at all:
First, an increase of the chip operation voltage allowing shorter cycle times to avoid resonance. This, however, implies more power dissipation, which is not desired at all.
Second, stretching the system cycle time to avoid resonance. This however reduces the system performance, which also is not desired.
BRIEF SUMMARY OF THE INVENTION
It is thus an objective of the present invention to provide a method and system for reducing delta I-noise in digital circuit systems.
According to the broadest aspect of the present invention a method and respective system is disclosed in a general approach for reducing delta-I noise in a digital circuit system comprised of a plurality of activity units being connected to a DC-supply voltage, in which method and system respectively, the operation of said digital circuit system may excite high-frequency fluctuations of a total supply current I (delta-I), and a respective resulting fluctuation of the supply voltage. Said method is characterized by the steps of:
a) maintaining a circuit system-specific catalogue storing the current consumption and delta-I for each of said activity units in its operational state,
b) continuously monitoring the actual current consumption of the total of said activity units,
c) determining critical operation conditions to be caused by an immediately imminent excess fluctuation of the supply voltage resulting from an immediately imminent delta-I demand, the excess quantity being defined relative to a predetermined set tolerance band for the total current I,
d) dependent of the quantity of the imminent delta-I demand selecting a subset of said activity units with a respective current delta-I demand, for either
aa) temporarily delaying their begin of activity in case of an imminent supply voltage drop, or
bb) temporarily continuing their activity with a predetermined, activity-specific No-Operation (NO-OP) phase in case of an imminent supply voltage rise.
During the physical system packaging design various power supply loop resonance frequencies (f_crit), the corresponding critical duty factor ranges (T=1/f_crit) and a maximum allowed single total delta-I demand (i_crit) value are determined by simulation and are coded into a system specific catalo
Becker Wiren Dale
Frech Roland
Garben Bernd
Harrer Hubert
Huber Andreas
Gonzalez Floyd A.
International Business Machines - Corporation
Lauture Joseph
Young Brian
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