Fishing – trapping – and vermin destroying
Patent
1989-07-11
1990-10-02
Hearn, Brian F.
Fishing, trapping, and vermin destroying
357 40, 364490, H01L 2170
Patent
active
049607243
ABSTRACT:
A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.
REFERENCES:
patent: 4602339 (1986-07-01), Aihara et al.
Hayashi Terumine
Natabe Takashi
Takei Takayuki
Watanabe Shoichi
Hearn Brian F.
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
Thomas T.
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