Method for decreasing the discharge time of a flash EPROM cell

Static information storage and retrieval – Floating gate – Particular biasing

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36518533, G11C 700

Patent

active

055965318

ABSTRACT:
The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell. In yet another aspect, a method for decreasing a discharge time of a Flash EPROM cell while reducing punchthrough includes the steps of providing a high energy core cell implant of a p type dopant into a substrate of the cell, wherein the core has a doping concentration profile with a low dopant concentration at a surface of the core to reduce UVV.sub.t and a high dopant concentration at lower than the surface to reduce punchthrough.

REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 5440158 (1995-08-01), Sung-Mu

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