Method for decreasing penalty resulting from a cache miss in mul

Details Method for decreasing penalty resulting from a cache miss in mul Method for decreasing penalty resulting from a cache miss in mul

1994-08-04

1996-11-19

Chan, Eddie P.

395464, 395471, 395495, G06F 1208

Patent

active

055772277

ABSTRACT:
A computing system includes a processor, a main memory, a first level cache and a second level cache. The second level cache contains data lines. The first level cache contains data line fragments of data lines within the second level cache. In response to a processor attempt to access a data word, a cache controller searches for the data word in the first level cache. When a first level cache miss results from the attempted access, a search is made for the data word in the second level cache. When a second level cache miss results a new data line, which contains the data word, is fetched from the main memory. Concurrently, the cache controller determines which entries of the first level cache are invalid. Once the new data line is fetched from the main memory, the new data line is placed in the second level cache, replacing the second level victim cache line. In addition, as many data line fragments as possible from the new data line are placed into invalid entries in the first level cache. One of data line fragments from the new data line placed into the first level cache includes the data word.

REFERENCES:
patent: 4463420 (1984-07-01), Fletcher
patent: 4464712 (1984-07-01), Fletcher
patent: 4722047 (1988-01-01), Chan et al.
patent: 4774654 (1988-09-01), Pomerence et al.
patent: 4823259 (1989-04-01), Aichelmann, Jr. et al.
patent: 4972316 (1990-11-01), Dixon et al.
patent: 5136700 (1992-08-01), Thacker
patent: 5214765 (1993-05-01), Jensen
patent: 5249282 (1993-09-01), Segers
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5361391 (1994-11-01), Westberg
J. L. Baer, W. H. Wang, Multilevel Cache Hierarchies: Organizations, Protocols and Performance, Journal of Parallel Distributed Computing, vol. 6, 1989, pp. 451-476.
W. H. Wang, J. L. Baer and H. Levy, Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, Proceedings of the 16th Annual International Symposium on Computer Architecture, 1989, pp. 140-148.
J. L. Baer, W. H. Wang, On the Inclusion Properties for Multi-Level Cache Hierarchies, Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988, pp. 73-80.

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