Static information storage and retrieval – Hardware for storage elements
Reexamination Certificate
2002-07-29
2004-04-06
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Hardware for storage elements
C365S191000
Reexamination Certificate
active
06717832
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for communication between a plurality of semiconductor modules, in particular semiconductor memory modules, and a controller module via a common bus system. A respective semiconductor module is selected and activated by the controller module by an appropriate command and a respective chip select signal fed separately to the semiconductor modules. The invention also relates to a semiconductor module, in particular a semiconductor memory module, which is configured for this purpose.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for data communication between a plurality of semiconductor modules and a controller module and a semiconductor module configured for that purpose that overcome the disadvantages of the prior art devices and methods of this general type, in which time conflicts and the resulting reduction in the bus efficiency and the data throughput rate are avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for communicating between a controller module and memory modules, including a first memory module and a second memory module, through a common bus system. The method includes outputting from the controller module a command signal and chip select signals including a first chip select signal and a second chip select signal fed to the memory modules for selecting a respective memory module. The first memory module receives both the first chip select signal and the second chip select signal and the second memory module receives the second chip select signal. A bus signal line termination is activated for terminating data to be transmitted from the controller module to both of the memory modules only in the first memory module as soon as the first memory module functioning as a monitoring memory module registers one of the chip select signals.
In the communications method according to the invention, one of the memory modules can monitor the chip select signal sent by the controller module to another semiconductor module, and to itself and activate its own signal line termination if it has detected the chip select signal.
As a result of the monitoring semiconductor module monitoring, at its second chip select input, the chip select signal which is fed to the other semiconductor module, the monitoring semiconductor module can listen in to the commands sent to the adjacent module and distinguish them from “its own” commands sent to it by the controller module. The monitoring makes it possible for the one memory module to carry out functions that are based on the activity in the second semiconductor module. By virtue of the fact that one of the two semiconductor modules forms the active signal termination for both semiconductor modules, the time conflict described above and the pause in the data stream can be eliminated.
So that the active line termination can be applied with correct timing, the monitoring module must know when the monitored semiconductor module has received a write command. This information can be determined by linking to the chip select input of the monitored semiconductor module the command signals that are fed jointly to the two semiconductor modules by the controller module. In this way, the monitoring semiconductor module knows when the monitored memory module has received a write command, and can thus activate the line termination, or if it is already activated, leave the line termination activated. As a result, the time conflict brought about by the switching over of the line termination on the data bus can be avoided if the switching over of the respective memory module addressed for the write data takes the form of switching from the first memory module to the second or from the second memory module to the first.
The additional expenditure on circuitry which is necessary in the semiconductor modules in order to carry out the method according to the invention is minimal as the reaction of the monitoring semiconductor module to the write command for the monitored semiconductor module is part of the normal activity of the monitoring module in reaction to its own write command. Thus, each semiconductor module needs, apart from the additional second chip select input for linking it to the write command, that is to say for the chip select monitoring circuit, only a second copy of internal circuit units which are already present in the semiconductor module.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory module. The memory module contains an interface circuit for receiving data and commands from a common controller module via a common bus system configured for connecting two such semiconductor memory modules to the controller module. The interface includes an active line termination circuit, a first chip select input provided for selecting a respective memory module by the controller module, a first chip select monitoring circuit connected to the first chip select input, a second chip select input, and a second chip select monitoring circuit connected to the second chip select input. It being possible to connect the second chip select input to a first chip select input of a second memory module, and after the second chip select monitoring circuit registers a chip select signal received at the second chip select input the second chip select monitoring circuit activates the active line termination circuit to perform a line termination of data signals transmitted by the common controller module.
In accordance with an added feature of the invention, the semiconductor memory module is a SDRAMs or a SGRAM.
In accordance with another feature of the invention, the interface has a programmable mode register into which it is possible to program information indicating if the second chip select monitoring circuit monitors the second chip select input, and if the active line termination circuit is activated in response to receiving the chip select signal in the second chip select monitoring circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for data communication between a plurality of semiconductor modules and a controller module and a semiconductor module configured for that purpose, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5621685 (1997-04-01), Cernea et al.
patent: 6009494 (1999-12-01), Pawlowski
patent: 6393504 (2002-05-01), Leung et al.
patent: 197 34 554 (1999-02-01), None
Johnson Bret
Nygren Aaron
Greenberg Laurence A.
Infineon - Technologies AG
Le Thong Q.
Locher Ralph E.
Stemer Werner H.
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