Boots – shoes – and leggings
Patent
1989-05-15
1992-06-02
Hecker, Stuart N.
Boots, shoes, and leggings
364DIG1, G06F 1208
Patent
active
051194856
ABSTRACT:
A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.
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"Boost DRAM performance with SRAM caching scheme," Electronic Design, Jim Langston, Jun. 9, 1988, pp. 107-112.
Ledbetter, Jr. William B.
Reininger Russell A.
Elmore Reba I.
Hecker Stuart N.
King Robert L.
Motorola Inc.
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