Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-03-22
2011-03-22
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S053000, C716S055000, C716S119000, C700S098000, C700S120000, C700S121000, C438S045000, C438S217000, C438S289000, C438S369000, C438S510000
Reexamination Certificate
active
07913195
ABSTRACT:
According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor are controlled. An overlapping area of a gate electrode and an element region of a certain group is extracted from mask layout data. The overlapping area is expanded to determine the shape of a mask used in injecting impurity in a channel layer. The data on the mask shape is then added to the mask layout data.
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Fujitsu Patent Center
Fujitsu Semiconductor Limited
Kik Phallaka
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