Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-08-30
2011-08-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S104000, C716S136000
Reexamination Certificate
active
08010918
ABSTRACT:
The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localized in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of the HDL description files in an automatic sequential manner and without relational or functional analysis of the identified memory elements, ensuring that at least one so-called SCAN channel is obtained during the synthesis of the system, linking the memory elements.
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Bowers Brandon W
Chiang Jack
Clark & Brody
Institut National Polytechnique de Grenoble
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