Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-10-04
2001-07-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S598000, C438S599000, C438S671000
Reexamination Certificate
active
06261918
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a method for creating metal alignment marks in the manufacture of semiconductor integrated circuits. More particularly, the present invention relates to a method in which two layers of marks are positioned in perpendicular direction to one another in order to create alignment marks for properly aligning mask layers in the formation of integrated circuits where the alignment marks are preserved after chemical mechanical polishing processes utilized during the formation of an integrated circuit. The metal alignment mark creation of the present invention does not require removal of metals from the alignment marks in order to see the alignment marks for proper aligning of mask layers.
Microchip fabrication involves a series of processes such as layering, patterning and doping to create integrated circuits and semiconductor devices in and on a semiconductor wafer surface. As opposed to “non-integrated” circuits in which elements such as transistors, diodes, resistors, etc., are fabricated separately and then assembled, “integrated” circuits comprise elements which are fabricated and interconnected on a single chip of semiconductor material. In fabricating integrated circuits, thin layers of material such as insulators, semiconductors or conductors, are deposited on the surface of the semiconductor wafer by a variety of techniques including chemical vapor deposition, physical vapor deposition, evaporation and sputtering.
After the formation of a layer, a process known as patterning is performed in which the pattern in a reticle or photo mask is transferred to a wafer to identify areas to be doped or selectively removed from the layers. Patterning, also known as photomasking, requires two steps, namely (1) the positioning or alignment of the required image on the wafer surface and (2) the encoding of the image in the photoresist layer from an exposing light or other radiation source. The final wafer pattern is typically generated from several photomasks which are sequentially applied to the wafer. Accordingly, correct alignment of the image patterns and establishment of the precise image dimensions in the photoresist are absolute requirements for the proper functioning of the semiconductor devices in integrated circuits.
Aligner systems are composed of two major subsystems, one for correctly positioning the pattern on the wafer surface and the other for exposing the pattern on the wafer surface by directing radiation rays from the permanent exposure source to the wafer surface. Steppers involve stepping images directly from a reticle onto a wafer surface. A reticle is a reproduction of the pattern to be imaged on the wafer (or mask) by a step-and-repeat process where each chip is aligned and exposed, and the aligner steps to the next location. The actual size of the pattern on the reticle is usually several times the final size of the pattern on the wafer.
Advantages of using steppers and step-and-scan include the precise matching of largerdiameter wafers, improved resolution due to the smaller area being exposed at each time of exposure thereby lessening vulnerability to dust and dirt, and easier fabrication of oversized reticles so that the patterns to be imaged are easily and accurately produced. However, in order to facilitate production of semiconductor devices and integrated circuits using steppers and step-and-scan, automatic alignment systems are needed. Without automatic alignment, an operator would have to individually align several hundred die on a wafer at a productive rate, which is nearly impossible. Automatic alignment is accomplished by passing low-energy laser beams through alignment marks on the reticle and reflecting them off corresponding alignment marks on the wafer surface. Resulting signals arc analyzed and information is fed into a computer which moves the wafer around until the wafer and reticle are aligned. After alignment, the images are then placed in the photoresist by sequentially exposing each die pattern across and down the wafer.
This alignment of two features on successive layers is easily accomplished, especially in cases where the preceding layer is transparent or translucent, thereby allowing alignment marks formed within an underlying wafer to be optically detected so that the mask can be properly aligned through the transparent oxide layer for the contact and via holes. Nevertheless, there are many cases in which the alignment of non-successive layers is necessary where the intervening layer is opaque. Metal layer alignment is an example of such an instance where it may be necessary to align a mask to a mark on a layer that is covered with an opaque metal layer.
Further, alignment marks may be effected by subsequent processing of the pattern transferred to the wafer surface thereby rendering it more difficult to be observed for alignment. For example, a metallization layer, such as tungsten, for example, used for via interconnection, relies on the replication of a sharply-defined edge produced at the contact or via hole etching prior to the tungsten deposition. However, the conventional chemical mechanical planarization of the surface of the wafer that is performed during the conventional process of tungsten eliminates the sharply-defined edges of the alignment marks.
Other prior art processes have set forth methods for producing consistent alignment marks or recovering alignment marks during the formation of integrated circuits in semiconductor devices. For example, one known industry approach to eliminating the dishing impact on alignment marks is to remove the metal on top of the alignment marks using a “clear out window” approach. This “clear out window” process involves (1) coating, exposing and developing a “clear out window” to open the alignment mark area, (2) metal etching to remove the metal and resist strip, and (3) returning to the first step to coat, align, expose and develop the metal layer. The steps of coating, exposing and developing the “clear out window” to open the alignment mark area and metal etching to remove the metal and resist strip must occur for each metal layer that is processed. This results in increased costs and the need for additional equipment. The repeated steps required for the metal removal process impacts cycle time and results in an increase in costs of up to $27 or more per wafer per metal layer that is removed. Further, in order to carry out the metal removal process, additional equipment, such as stepper, etcher and resist strip tools, must be purchased to carry out the process.
Another known industry approach for preserving alignment marks is a shadow tab process which utilizes extended tabs during metal deposition to block out metal deposition on top of the alignment marks. Due to the use of extended tabs used in this process, metal shadowing causes die loss at the shadow tab sites and the dies located near the shadow tab sites. The greater the number of tabs used, the greater the number of die losses that are incurred. Typically, one can expect a loss of 4-12 dies per wafer when four tabs are used. In addition to the die loss problem, the shadow tab process also creates metal sticking problems in the metal deposition systems which require more frequent preventative maintenance during wafer processing. In addition, the die loss and increased preventative maintenance results in equipment downtime.
Other prior art has dealt with obtaining consistent alignment mark profiles and recovering alignment marks after chemical mechanical polishing. For example, U.S. Pat. No. 5,904,563, issued to Yu, discloses a method for metal alignment mark generation where the contact hole via mask used in the manufacture of semiconductor integrated circuits is modified to produce a plurality of lines and spaces adjacent to the edge of an alignment mark in the via hole pattern. The line-space pattern is etched simultaneously with the contact via holes and allows for the regeneration of the alignment mark after tungsten deposition and planarization of the w
Conexant Systems Inc.
Gurley Lynne A.
Niebling John F.
Snell & Wilmer L.L.P.
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