Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
1999-05-04
2001-12-04
Kim, Kenneth S. (Department: 2183)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C703S015000, C712S240000
Reexamination Certificate
active
06327559
ABSTRACT:
FIELD OF THE INVENTION
In general this invention relates to testing of electrical components and, particularly, to testing and verification of a design for microprocessor logic, and provides a method for creating a simulation environment for enhanced logic verification of a Branch History Table (BHT).
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, New York, U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
Within IBM for S/390 development testing by running a program test, a kind of processor level testing can be used to verify architectural compliance of the Branch History Table or BHT, but such testing, before this invention, will not necessarily catch problems where the BHT logic fails to perform as intended. There are no known patents which deal with the verification of a branch history table, so those in the art have been previously left without any teaching. Accordingly, I have described herein a new method for verification of the Branch History Table described herein and believe its use will be desirable.
SUMMARY OF THE INVENTION
This invention describes a method for verification of instruction processing units such as a Branch History Table (BHT) of a machine design. The verification method, according to the preferred embodiment described to drive a Branch History Table, comprises two components. A first component comprises the steps of a method for creating instruction streams for controlling the stress on branch history table logic. The second component comprises a method for pre-loading the branch history array to allow for interesting simulations at the beginning of the test.
The method for creating instruction streams allows user control over the parameters that are of interest to the branch history logic, such as the rate of branches in the instruction stream and the branch type. By varying these parameters in different tests, the user can stress different corners of the logic and easily manipulate the test environment.
The method for pre-loading the branch history array gives varying control over the initial state of the branch history table as the test begins. This method allows the test to have a “history” at the beginning of the simulation that otherwise would take many simulation cycles to develop. This method gives user control over interesting simulation scenarios at the onset of the testing.
These methods can be combined and varied, by the steps described, to provide useful testing of the BHT environment and the design that is being verified by the method described to provide architectural compliance for a machine design. This is particularly effective for the corner conditions of the designed logic.
REFERENCES:
patent: 5515527 (1996-05-01), Kurashita
patent: 5673425 (1997-09-01), Iwashita
patent: 5995915 (1999-11-01), Reed et al.
patent: 6006028 (1999-12-01), Aharon et al.
patent: 6011830 (2000-01-01), Sasiu et al.
Augspurger Lynn L.
International Business Machines - Corporation
Kim Kenneth S.
LandOfFree
Method for creating a simulation environment for enhanced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for creating a simulation environment for enhanced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for creating a simulation environment for enhanced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561145