Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2003-07-28
2004-09-21
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S076000, C438S433000, C438S524000, C438S724000
Reexamination Certificate
active
06794219
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of image sensors and, more particularly, to such image sensors having a lateral overflow drain substantially underneath a thick field dielectric.
BACKGROUND OF THE INVENTION
In full frame type, charge-coupled device (CCD) image sensors, lateral overflow drain (LOD) structures formed along the sides of the vertical CCD shift registers to provide means for conducting excess electrical charges away from the imaging area are well known in the art, (e.g., U.S. Pat. No. 5,130,774 issued Jul. 14, 2002). Such removal is necessary to prevent the image defect known as blooming in the CCD pixels, in which the column becomes either partially or completely flooded with charge thereby destroying the intended image. Referring to
FIG. 1
, an illustration of a conventional lateral overflow drain structure is shown in cross section drawn at the center of two adjacent columns. To form the LOD, an implant consisting of n-type impurities is made into the p-type substrate at the edge of the device active area and is typically positioned adjacent to a region of thick field oxidation that has been grown to provide electrical isolation between the vertical CCD columns of the imaging area and the LOD. Electrical isolation is also provided and enhanced by a p-type implant made under the field oxidation. Upon illumination of the array, photogenerated electrical charge is collected in the implanted n-type buried channel regions. To prevent blooming at high illumination levels, a region of the buried channel that connects the CCD to the LOD is compensated with p-type impurities to form an electrostatic potential barrier to the LOD. This barrier height is adjusted so that it is lower than the barriers to adjacent pixels. Thus, excess electrical charges, that would normally overfill the buried channel regions and bloom up and down the columns, instead find an outlet over the LOD barrier into the n-type LOD drain where they can be safely conducted away from the imaging area. A plot of the electrostatic potential, or channel potential, versus position for the structure under typical operational condition appears in FIG.
2
.
In order to provide a sufficient level of conductivity to handle the large amounts of overflow current typically required for high-performance imaging applications, it is usually necessary to introduce a large dose of n-type impurities to form the LOD. However, it is found from numerical simulation of the device shown in
FIG. 1
, that a practical limitation on the amount of n-type impurities that can be implanted (and therefore an upper bound on the lateral overflow drain conductivity) is reached when the electrical fields produced at the silicon surface become high enough to cause electrical breakdown of the LOD via the impact ionization mechanism (also known as avalanche breakdown) or via quantum mechanical band-to-band tunneling. In simple terms, electrical breakdown results in the generation of undesirably large electric leakage currents. The breakdown condition ordinarily is produced as the applied bias on the device electrodes is increased. It should be evident to those skilled in the art that the conditions for avalanche breakdown are most severe for the accumulation mode of operation U.S. Pat. No. 5,115,458 issued May 19, 1992, where the gate electrodes are placed at, say, −10 volts. Because the lateral overflow drain is biased at, say, 10 volts, a total of 20 volts is placed across the thin gate dielectric, with the highest electric field occurring at the silicon surface above the center of the lateral overflow drain implant. A representative plot of the surface electric field strength versus position is included in FIG.
1
.
To avoid this surface breakdown limitation, the drain can be placed underneath the thick field oxide that is typically used for channel-to-channel isolation between the vertical CCDs of these devices as described in U.S. patent Ser. No. 09/945,034, filed Aug. 31, 2001. By placing the field oxide layer over the lateral overflow drain (in place of the relatively thin gate dielectric), the surface electric field is reduced in inverse proportion to the thickness. In implementing such a device, the lateral overflow drain should be aligned to the edge of the field oxide layer. If the drain is not fully covered by the field oxide layer, its breakdown voltage will be reduced as limited by the portion of the drain that protrudes out beneath the thinner gate dielectric. If, on the other hand, the drain is placed too far laterally underneath the field oxide layer, connection to it via the buried channel may be lost. This latter problem could arise because the buried channel is typically self-aligned to the field oxide edge by implanting it after the field oxide growth. This may render the structure nonfunctional. Although the latter limitation could be eliminated by implanting the buried channel prior to the field oxide growth, the former problem would still exist.
Consequently, a need exists for overcoming the above-described shortcomings by providing a process wherein the lateral overflow drain is underneath and self aligned to one edge of a thick dielectric layer.
SUMMARY OF THE INVENTION
The present invention is directed towards overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in a method for creating a self aligned, under-the-field-oxide lateral overflow drain, anti-blooming structure in a charge-coupled device, the method comprising the steps of (a) providing a substrate of a first conductivity type; (b) providing a layer of silicon dioxide on the substrate; (c) providing a layer of silicon nitride on the silicon dioxide layer; (d) providing a first masking layer on the silicon nitride layer and having an opening in the first masking layer of a dimension which substantially equals a dimension of a subsequently implanted channel stop of the first conductivity type; (e) etching away the exposed silicon nitride within the opening in the first masking layer; (f) implanting ions of the first conductivity type through the first masking layer and into the substrate for creating the channel stop and removing the first masking layer; (g) growing the silicon dioxide layer so that the channel stop is spanned by a thickest field silicon dioxide layer in the etched away portion; (h) patterning a second masking layer having an opening adjacent the channel stop with a dimension substantially equal to a dimension of a subsequently implanted lateral overflow drain of a second conductivity type; (i) etching away the exposed silicon nitride within the opening in the second masking layer; (j) implanting the second conductivity type for forming the lateral overflow drain and removing any remaining masking layer; and (k) growing the silicon dioxide layer so that a thicker silicon dioxide forms spanning the lateral overflow drain and the thickest silicon dioxide layer forms spanning the channel stop.
An alternative embodiment of the present invention eliminates the step of growing the first thickest field silicon dioxide layer in (g) above by using the etched away portion of the silicon nitride layer as a mark to which a subsequent lateral overflow drain region can be aligned to, and by growing a thick silicon dioxide layer spanning both the lateral overflow drain and the channel stop at the same time in (k). This simpler, alternative embodiment can be used provided that the mask alignment tool is capable of recognizing alignment marks formed by etched away portions of the silicon nitride layer, only.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
Advantageous Effect of the Invention
The present invention has the following advantages of providing self-alignment of one side of the later
Doan Hung Q.
Stevens Eric G.
Brewster William M.
Eastman Kodak Company
Watkins Peyton C.
LandOfFree
Method for creating a lateral overflow drain, anti-blooming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for creating a lateral overflow drain, anti-blooming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for creating a lateral overflow drain, anti-blooming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3200345