Method for creating a high speed scan-interconnected set of flip

Details Method for creating a high speed scan-interconnected set of flip Method for creating a high speed scan-interconnected set of flip

1995-12-04

1998-02-10

Nguyen, Hoa T.

Excavating

G01R 3128

Patent

active

057177007

ABSTRACT:
The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.

REFERENCES:
patent: 4879718 (1989-11-01), Sanner

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