Method for creating a die shrink insensitive semiconductor...

Details Method for creating a die shrink insensitive semiconductor... Method for creating a die shrink insensitive semiconductor...

2001-08-07

2002-12-03

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S784000

Reexamination Certificate

active

06489674

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to components useful in making electrical connections to microelectronic elements such as semiconductor chips, and to methods of manufacturing such components.
FIG. 1
shows a specific semiconductor package marketed by the present assignee under the registered trademark &mgr;BGA. In short, the figure shows semiconductor chip having contacts
110
on a face surface
120
. A flexible, dielectric substrate
130
overlies and is juxtaposed with the face surface
120
of the chip
100
. The substrate
130
has a first surface
150
facing away from the chip
100
, and a second surface
160
, facing towards the chip
100
. The substrate
130
further has conductive leads
170
running along the second surface
160
. Each lead has a connection section
180
extending across a bonding window
190
. The connection sections
180
are releasably attached to the substrate, as described in U.S. Pat. Nos. 5,489,749 and 5,629,239 hereby incorporated by reference herein. Each lead terminates in a conductive terminal
200
which is exposed at or overlies the first surface
150
of the substrate
130
. A compliant layer
140
is disposed between the substrate
130
and the face surface
120
of the chip
100
. In this embodiment, the compliant layer
140
takes the form of a plurality of compliant pads
140
, as described in U.S. Pat. No. 5,659,952 hereby incorporated by reference herein. The leads are detached and bonded to respective chip contacts
110
, such as by thermocompression or ultrasonic bonding techniques. The bond windows are then covered by a coverlay or soldermask (not shown) and a liquid encapsulant
210
is dispensed or injected into and between the substrate
130
and the chip
100
, as described more fully in U.S. patent application Ser. No. 08/726,697 incorporated by reference herein. The encapsulant
210
is then cured and solder balls
220
are connected to the terminals
200
and the package is cut to size, as shown, for future connection to a printed wiring board (“PWB”).
As the chip
100
heats up and cools down in operation, it expands and contracts at an inherent rate, called its coefficient of expansion (“CTE”). The CTE of silicon is approximately 2.7 to 3.0 parts per million per degree Celsius. As the chip heats up and cools down in operation, the underlying PWB also heats up and cools down (and thereby expands and contracts) in response to the chip
100
. However, the CTE of standard epoxy/fiberglass PWBs is approximately 15 to 20 parts per million per degree Celsius causing a mismatch in the expansion and contraction between the chip and the PWB. The construction of the package shown in
FIG. 1
mechanically decouples the chip from the underlying PWB to allow for movement of the terminals
200
/solder balls
220
with respect to the chip contacts
110
thereby allowing the chip to expand and contract at one rate and the PWB to expand and contract at another rate without the mechanical connection fatiguing and becoming unreliable due to the thermal mismatch, as explained more fully in U.S. Pat. No. 5,679,977 hereby incorporated by reference herein. In this type of chip package construction, it is typically better, from a reliability stand-point, for the connection section
180
of the leads
170
to have a gradual radius of curvature both at the heel of the connection section
180
(near where it connects to the chip contact
110
) and at the shoulder of the connection section
180
(near where it connects to the substrate
130
). Such a gradual radius of curvature better ensures that the connection section
180
does not hinge about a single point or area as it is flexing in response to the thermal mismatch phenomenon described above. To create such a gradual radius of curvature for the connection sections
180
, the connection sections
180
must be a certain minimum length which depends on the stand-off (or vertical height) from the face surface
120
of the chip
100
to the second surface
160
of the substrate
130
. This connection section
180
minimum length also sets the allowable minimum dimension (D
W
) for the bonding window
190
. Likewise, the minimum dimension D
W
for the bonding window
190
limits the amount of area (D
S
) on the first surface
150
of the substrate
130
that is available for terminals
200
. Typically, the preferred terminal
200
center to center distance (or “pitch”) is somewhere between 0.8 and 0.65 millimeters with a typical terminal size of 275 &mgr;m to 300 &mgr;m and a solder ball
220
diameter of approximately 300 &mgr;m to 350 &mgr;m. On some package designs, it is permissible to use a terminal pitch of 0.5 millimeters which allows more terminals to be placed in the same substrate area D
s
. The major constraint on using a pitch of 0.5 millimeters or below is that most inexpensive PWBs cannot be wired to receive contacts at such a fine pitch so more expensive substrates must be used.
FIGS. 2 and 3
show fragmentary side views of a chip package similar to the package shown in FIG.
1
. In
FIG. 2
, the length of the bonding window
190
a
and therefore the connection section
180
a
have been shortened to D
W1
when compared to the bonding window
190
b
(D
W2
) and connection section
180
b
of FIG.
3
. As explained above, this shorter connection section
180
a
has a larger radius of curvature at the heel and shoulder of the connection section
180
a
and may also have a less reliable response to thermal cycling. In many packaging applications, the shorter connection section shown in
FIG. 2
may have acceptable reliability characteristics. However, it is preferred to have the longer connection section
180
b
of the type shown in
FIG. 3
because it has been found that such leads are more reliable over a longer period of time and/or under greater thermal mismatch conditions.
Another issue with respect to a larger bonding window
190
b
(D
W2
) is that the bonding window
190
may get in the way of the locations of the terminals
200
as the semiconductor manufacturer shrinks the size of its chips which causes the locations of the chip contacts to move. Semiconductor manufacturers fabricate a plurality of semiconductor chips en mass in a unitary, planar structure called a wafer. The chips are typically separated from each other later prior to the packaging operation. Typically, a semiconductor manufacturer will endeavor to take its original design for a particular semiconductor chip
100
and change it so that the same or better functionality are placed into a smaller first surface
120
area. This allows the semiconductor manufacturer to fit more chips into a single wafer. Since the cost of processing wafers is approximately constant, this process of reducing the chip size provides more chips for less manufacturing cost per chip. As a general rule of thumb, most chip shrinks are about 20% (or more) smaller than the size of the original chip and typically the chip manufacturers only perform two or three chip shrinks before discontinuing a particular chip type in favor of a new design or technology; although, some chip makers perform more chip shrinks before going to a completely new chip design depending on the aggressiveness of the chip maker and the type of die.
As the chip shrinks and the chip contacts move inward from their original locations, the bonding windows
190
and connection sections
180
in the chip package shown in
FIG. 1
also have to move to compensate for the chip contact
110
movement. If the bonding windows need to be moved into the area D
S
on the first surface
150
of the substrate
130
that is occupied by the terminals
200
, the terminal pitch and arrangement may no longer be uniform with the last version of the chip package. This causes the PWB manufacturer to have to re-design the PWB to account for the movement of the terminals
200
/solder balls
220
. One method of compensating for the problems that are encountered because of a chip shrink is to place the chip face up on the supporting substrate so that the chip contacts fa

Affiliated with

Also associated with

Rating

Method for creating a die shrink insensitive semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for creating a die shrink insensitive semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for creating a die shrink insensitive semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2949685