Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2001-03-23
2003-07-01
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S532000, C702S089000
Reexamination Certificate
active
06586924
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a timing calibration method for an IC tester for testing ICs such as memories and an IC tester equipped with a calibration function using the calibration method.
PRIOR ART
FIG. 11
depicts the general outlines of a commonly known IC tester. Reference character TES designates generally the IC tester. The IC tester TES comprises a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logic comparator
115
, a driver group
116
, a comparator group
117
, a failure analysis memory
118
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
and a device power supply
123
.
The main controller
111
is formed, in general, by a computer system and operates under the control of a test program prepared by a user, controlling the pattern generator
112
and the timing generator
113
. The pattern generator
112
generates test pattern data, which is converted by the waveform formatter
114
to a test pattern signal that has an actual waveform, and the test pattern signal is provided to and stored in an IC under test
119
after being voltage-amplified by the driver group
116
to a waveform having an amplitude value set in the logical amplitude reference voltage source
121
.
For example, when the IC under test
119
is an IC memory, a response signal read out of the IC under test
119
is compared by the comparator group
117
with a reference voltage from the comparison reference voltage source
122
to decide the logic level (voltage of a logic “H”, voltage of a logic “L”) of the response signal. The logic level thus decided is compared by the logic comparator
115
with an expected value that is output from the pattern generator
112
; if a mismatch is found between the logic level and the expected value, it is decided that the memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory
118
for use in deciding, after completion of the test, whether the failed cell is repairable.
The timing generator
113
generates timing that defines the rise and fall timing of the waveform of the test pattern signal that is applied to the IC under test
119
, and the timing of a strobe pulse that defines the timing for logical comparison by the logic comparator
115
.
The respective timing is described in the user's prepared program so that at the user's intended timing the IC under test
119
can be actuated and tested for normal operation.
A description will be given, with reference to
FIG. 12
, the general outlines of the timing generator
113
and the waveform formatter
114
.
FIG. 12
depicts the general configurations of the waveform formatter and the timing generator for generating a one-channel test pattern signal. The waveform formatter
114
can be formed by an S-R flip-flop, which is supplied at its set and reset terminals S and R with set and reset pulses P
S
and P
R
, respectively, to generate a test pattern signal TS that rises at predetermined timing T
1
and falls at predetermined timing T
2
. In
FIG. 12
the outputs from clock generators
113
A and
113
B are shown to be provided directly to the S-R flip-flop for the sake of brevity, but in practice, the connection of the outputs from a plurality of clock generators to the S-R flip-flop is controlled in real time in accordance with the waveform mode and pattern data.
The set and reset pulses P
S
and P
R
are generated by the pair of clock generators
113
A and
113
B. The generation timing of the set and reset pulses P
S
and P
R
by the clock generators
113
A and
113
B is defined by pieces of delay data DY
S
and DY
R
available from a delay data memory
113
C.
The delay data memory
113
C is accessed with an address signal that is provided from an address counter
113
D. The address counter
113
D generates an address signal whose address is incremented by one for each test cycle TS
RAT
after the start of testing; based on the address signal, an address assignment is made for each test cycle TS
RAT
during the test period, then delay data preset for each test cycle TS
RAT
is read out, and the read-out delay data is set in the clock generators
113
A and
113
B, which generate the set pulse P
S
and the reset pulse P
R
in accordance with the delay data.
FIGS. 13A-13E
show how the above operations are carried out. The set pulse P
S
is generated at timing delayed, by given delay data DY
S1
, behind, for instance, the rise timing of a rate clock RAT that defines the test cycle TS
RAT
, and generates the reset pulse P
R
at timing delayed behind the rise timing of the rate clock RAT by delay data DY
R1
, thereby generating the test pattern signal TP of a pulse width corresponding to the time difference T
PW
between the set and reset pulses P
S
and P
R
(see FIG.
13
E). The resolution for setting the set and reset pulses P
S
and P
R
is defined by the pulse interval of a clock CK depicted in FIG.
13
B.
From the above it will be understood that the test pattern signal TP can be set to rise and fall at arbitrary timing within the test cycle TS
RAT
.
Next, the operation of the comparator group
117
will be described. The comparator group
117
performs:
(a) an operation of deciding the logic of the response signal from the IC under test
119
by comparing it with a predetermined reference level at predetermined timing and capturing the decided logical value; and
(b) an operation of measuring the timing of the rise or fall of the response output signal TX.
FIGS. 14A-14F
are explanatory of the operation (a). In the case of the operation (a), the comparator sets the timing of a strobe pulse STB at the timing when the response output signal TX ought to arrive, and captures the logical value of the response output signal TX at the set timing of the strobe pulse STB. In the
FIG. 14
example, since the strobe pulse STB is set in the H-logic period of the response output signal TX, the comparator captures the H logic that is the result of the logic decision as shown in FIG
14
D. Accordingly, when the expected value in this test cycle is H as depicted in
FIG. 14
, the result of the logical comparison by the logic comparator
115
is decided to be OK (good) as shown in FIG
14
F.
FIGS. 15A-15E
are explanatory of the operation (b). In the case of measuring the timing of the rise and fall of the response output signal TX, the phase of the strobe pulse STB that is applied to the comparator
17
is shifted for each test cycle TS
RAT
within the range of the test cycle TS
RAT
or within the range several times longer than the test cycle, the logical value of the comparator output varies at the timing of the strobe pulse, and the rise timing and fall timing of the response output signal are decided based on the timing of the strobe pulse at the time the state of the logical decision output reverses as depicted in FIG.
14
D.
From the description given above with reference to
FIGS. 11
to
15
, it will be understood that the conventional IC tester has the capabilities of arbitrarily setting the generation timing of the test pattern signal and measuring the timing of the rise and fall of the response output signal TX from the IC under test.
The IC tester performs a timing calibration for in-phase application of test pattern signals to respective pins of the IC under test and a timing calibration for in-phase reading of response output signals from the IC under test into the IC tester.
A conventional method of timing calibration adopts a scheme that adjusts the delay times of variable delay circuits inserted in signal paths of respective pins to provide the same delay time on the signal paths.
The following two schemes are used to measure the delay time of the signal path.
(1) The time of reflection of the signal propagating along the signal path is measured through utilization of the timing measuring capability of the IC tester and the propagation dela
Okayasu Toshiyuki
Seki Nobusuke
Advantest Corporation
Cuneo Kamand
Gallagher & Lathrop
Hollington Jermele
Lathrop, Esq. David N.
LandOfFree
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