Data processing: artificial intelligence – Neural network – Structure
Reexamination Certificate
1999-05-12
2002-09-17
Black, Thomas (Department: 2121)
Data processing: artificial intelligence
Neural network
Structure
C341S155000
Reexamination Certificate
active
06453309
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for correcting an error in fast parallel analog-to-digital conversion, and to a mixed-mode corrector for error correcting to be used particularly in mobile communications devices, and to a parallel A/D converter which uses the corrector according to the invention.
2. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
From the prior art it is known fast parallel A/D conversion, or flash A/D conversion, wherein multiple comparators are used. In a conversion the resolution of which is N bits, 2
N
−1 reference signals are compared to the input signal, the reference signals being reference voltages having evenly increasing voltages. This technique is generally used in digital video equipment. The maximum speed of the converter is usually 15 to 300 million samples per second (MSPS).
FIG. 1
shows a prior-art parallel A/D converter. The series arrangement of resistors R
1
, R
2
, R
3
, R
4
and R
5
produces at the connection points steadily-rising reference voltages such that the values of the first resistor R
1
and last resistor R
5
in the ladder are half the values of intermediate resistors R
2
, R
3
and R
4
. Naturally there are more intermediate resistors if there are more comparators than shown in FIG.
1
. The second input signal of comparators IC
1
, IC
2
, IC
3
and IC
4
is an analog signal V
IN
to be converted which is compared to the reference voltages mentioned above. As the analog signal voltage V
IN
rises, the inputs of the comparators change one after the other from zero to one, i.e. from ground to operating voltage. Coder IC
5
latches the output signals of the comparators at sampling decision moments into memory and converts the information stored to an N-bit byte of binary code.
A problem with known fast A/D converters are conversion errors caused by inaccurate timing of state transitions of individual comparators. Inaccuracy can be caused by clock jitter, among other things, and it may result in non-simultaneous comparator state transitions. As the analog signal level changes, non-simultaneous comparison may cause bubbles in the so-called thermometer code produced by comparator outputs. This is illustrated in the table below which shows six erroneous sets of output signals in the first columns and the best guess in the last column on the right. A set comprises
14
comparator output signals. The correct voltage level is seen on the horizontal line.
TABLE 1
Examples of comparator errors in known A/D converter
0 0 0 0 1 0 0
0 0 1 0 1 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 0 0
1 0 0 1 0 0 0
0 1 1 0 1 1 1
1 1 1 0 1 1 1
1 0 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 0 1
1 1 1 1 1 0 1
1 1 1 1 1 0 1
In the first column of Table 1 the six lowest values are correct but the seventh value is erroneously zero, where ideal comparison would yield one. The next output is again one, but it should be zero. The six topmost outputs are correctly zeros. So, the A/D converter gives an inaccurate result. The next five columns show other possible error results. The last column on the right-hand side shows the ideal result. Several methods have been developed for error correcting in a parallel converter but they all involve a great number of logic circuits between the comparators and latch circuits.
It is an object of the invention to eliminate the above-mentioned inaccuracy with a reasonable amount of circuitry.
BRIEF SUMMARY OF THE INVENTION
The invention pertains to a method for correcting an error in a parallel analog-to-digital conversion wherein the error is caused by uncertainty in the reading of the states of parallel comparators in the converter, said uncertainty being the result of nonideality, such as non-simultaneous state latching. In accordance with the invention the error is corrected using a cellular nonlinear neural network.
The invention also pertains to a corrector for correcting an error in a parallel analog-to-digital converter, said corrector including parallel comparing elements which have uncertainty error, such as non-simultaneous state latching, in comparison state reading. According to the invention the corrector comprises a cellular neural net-work for reducing the error caused by the uncertainty of the output state control of individual comparing elements by estimating the real comparison result on the basis of the state of the comparing element and its neighbourhood.
The invention also pertains to a parallel A/D converter that includes a corrector for correcting an error in a parallel analog-to-digital converter, said converter including parallel comparing elements which have uncertainty error, such as non-simultaneous state latching, in comparison state reading. In accordance with the invention the corrector includes a cellular neural network for reducing the error caused by the uncertainty in the reading of the states of individual comparing elements by estimating the real comparison result on the basis of the state of the comparing element and its neighbourhood.
Preferred embodiments of the invention are described in the dependent claims.
An information processing network modelled after the biological neural network is called a neural network. Computing by means of neural networks is considerably faster than serial information processing as the former functions parallely such that information is processed simultaneously in each computing unit. Neural networks are also advantageously capable of generalizing calculation which is considerably more difficult using conventional computing algorithms.
The invention utilizes a cellular neural network designed mainly for image processing wherein one computing unit is called a cell. The cells are arranged into a certain shape, such as a two-dimensional quadrangular or hexagonal shape. The cellular neural network is one type of neural network, also known as the cellular nonlinear network (CNN). In a nonlinear cellular network the cells get their input from the cells of their neighbourhood, information from the different cells is weighted, and a dynamic state is formed in the cells. A linear or nonlinear function is used in a cell to form a cell state output. The cell output is taken to the neighbourhood cells as input, as described above. This way, the weighted outputs of the neighbourhood cells also affect the dynamic state of a cell. Thus, the cells have one input signal and one output signal and, in addition, connections to their specified neighbourhood.
A cellular neural network can be programmed to carry out various computational tasks by weighting the signals from the neighbourhood in various manners. Advanced cellular neural networks can be integrated more compactly than the original ones. Advanced cellular neural networks, such as the full signal range (FSR), high gain, positive range, and positive range high gain network, can be integrated on a microcircuit more compactly than the original ones. The invention is preferably implemented using a positive range high gain cellular neural network wherein the cell output signal level extends from zero to one and changes as a bistable state, i.e. such that no permanent intermediate states are specified.
The cellular neural network theory and cellular nonlinear network are also discussed in patent documents U.S. Pat. Nos. 5,140,670, 5,355,528 and 5,717,834.
In accordance with the invention, a on
Halonen Kari
Kananen Asko
Lindfors Saska
Paasio Ari
Black Thomas
Holmes Michael B.
Nokia Mobile Phones Limited
Perman & Greene, LLP
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