Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1998-04-23
2001-06-26
Aftergut, Jeff H. (Department: 1733)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C257S706000, C361S709000
Reexamination Certificate
active
06251706
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the cooling of a semiconductor device by the use of an infrared transparent heat slug that enhances the transfer of heat from the semiconductor device to a heat sink.
BACKGROUND OF THE INVENTION
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high speed integrated circuits. Flip chip technology is also known as control collapse chip connection (C4) technology. In C4 technology, the integrated circuit die is flipped upside down. This is opposite to how integrated circuits are packaged today using wire bond technology. By flipping the integrated circuit die upside down, ball bonds may be used to provide direct electrical connections from the bond pads of the die directly to a corresponding set of pads on a package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
FIG. 1
illustrates an integrated circuit die
102
that is housed in a cavity
105
of a PGA (Pin Grid Array) package
110
. The integrated circuit die includes a semiconductor substrate
103
having a top surface
107
and a back side surface
108
. The active regions
109
of the integrated circuit are formed from the top surface
107
of the of the semiconductor substrate
103
. Wire bonds
104
are used to electrically connect integrated circuit connections in integrated circuit die
102
through internal metal interconnects to the pins
106
of package substrate
110
. With the trend towards high speed integrated circuits, the inductance generated in the wire bonds
104
of the typical wire-bonded integrated circuit packaging becomes an increasingly significant problem.
FIG. 2
illustrates a C4 mounted integrated circuit die
202
that is electrically coupled to a PGA (Pin Grid Array) package
210
by ball bonds
204
. Die
202
includes a semiconductor substrate
203
that has a top surface
208
and a back side surface
207
. The active regions
209
of the integrated circuit are formed from the top surface
208
of the of the semiconductor substrate
203
. Because the bond pads of integrated circuit device
202
are located on the top-side surface
208
of the device, the die must be flipped upside down so that it may be attached to package
210
. In comparison with the wire bonds
104
of
FIG. 1
, the ball bonds
204
of integrated circuit device
202
provide more direct electrical connections between the integrated circuit device
202
and the pins
206
of package substrate
210
. As a result, the inductance problems associated with typical integrated circuit wire bond packaging technologies are minimized. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die, C4 technology allows connections to be placed anywhere on the integrated circuit die surface. This leads to a much cleaner and more efficient power distribution to the integrated circuit which is another major advantage of C4 technology.
During the silicon debug phase of a new product it is often necessary to probe certain internal portions of the integrated circuit in order to obtain important electrical data from the integrated circuit. Important data include measuring device parameters such as, but are not limited to, voltage levels, timing information, current levels and thermal information. Emissions from the backside of the die may also be measured to determine or locate a variety of defects, such as impact ionization, shorts, hot carrier effects, forward and reverse bias P-N junctions, transistors in saturation and gate oxide breakdown.
Present day debug process for wire bond technology is based on directly probing the metal interconnects on the chip front side with an electron beam (E-beam) or mechanical prober. Typical integrated circuit devices have multiple layers of metal interconnects and it is often difficult to access nodes that are buried deep in the chip. Usually other tools such as plasma etchers and focused ion beam systems must be used to mill away the dielectric and or metal above the node to expose metal nodes for probing. With C4 packaging technology, however, this front side methodology is not feasible since the integrated circuit die is flipped upside down making these internal metal nodes inaccessible.
In order to test and debug C4 mounted integrated circuit devices a number of optical-based testing methods, such as laser probing, have been developed that permit probing of internal portions of an integrated circuit through the back side of the C4 mounted devices. Since the active regions of the integrated circuit are located near the back side surface of the device, it is easier to access these regions through the silicon substrate for the purposes of laser or optical probing and/or for detecting photon emissions emitted from active devices. Since it is often difficult to access the active regions of an integrated circuit from the top surface of a wire-bonded integrated circuit device, it may be desirable to laser probe or detect photon emissions from the back side of a wire-bonded integrated circuit device. As such, the testing of internal nodes may be simplified with the use of an optical-based back side testing methodology. In such an instance, a portion of the package housing the integrated circuit must first be removed to expose the back side surface of the die's semiconductor substrate. Then optical based probing can be performed through the removed portion of the package housing.
During the testing or debugging of an integrated circuit device, it is generally desirable to operate the integrated circuit at its full operating capacity. Since the power density in modern microprocessors is typically very high, it is extremely important to remove heat created by the devices in order for the devices to maintain acceptable operating temperatures. If the temperature of the integrated circuit is not properly controlled, the performance of the circuit may be affected. In some instances, component degradation will occur if the temperature of the integrated circuit is not properly regulated. Thus, any information collected must be obtained with the device operating in its native packaged environment and with its temperature properly regulated. Otherwise, any information obtained may be useless.
FIG. 3A
illustrates a prior art approach to dissipating heat from a C4 mounted semiconductor device. Heat is removed from the back side surface
207
of semiconductor device
202
by passing an air flow
240
over a finned heat sink
230
that is thermally coupled to back side surface
207
. In some high power applications, heat is dissipated from semiconductor device
202
by attaching a thermally conductive heat slug
232
(e.g., a copper plate) to back side surface
207
and thermally coupling the heat slug to a heat sink. (See
FIG. 3B.
) In some instances, heat slug
232
is thermally coupled to a metal plate having a large thermal mass and a large heat transfer area. In other instances, heat slug
232
may be thermally coupled to a heat spreading plate by a heat pipe or some other low resistance thermal path.
As depicted in
FIG. 4A
, the removal of heat from a wire bonded semiconductor device
102
generally involves attaching a finned heat sink
130
to the bottom surface
112
of package
110
and passing an air flow
140
over the heat sink. A heat flow path is established across the back side surface
114
of semiconductor device
102
through package
110
and into heat sink
130
. A heat slug (not shown) embedded within package
110
thermally couples die
102
to heat sink
130
. Heat is carried away by the air flow
140
passing across finned heat sink
130
. In high power applications, a heat slug
130
may be attached to the bottom surface
112
of package
110
and then thermally coupled to a heat spreading plate or
Aftergut Jeff H.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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