Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-08-06
2001-04-10
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S166000
Reexamination Certificate
active
06215434
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of converting an analog input signal into a digital output signal comprising the steps of deriving a square wave duty cycle modulated by the analog input signal, of generating a clock synchronous sampling pulse and of sampling the duty cycle modulated square wave with the clock synchronous sampling pulse to generate the digital output signal.
An arrangement for carrying out such method has been proposed in applicant's earlier european patent application (PHN 16308). This patent application discloses an asynchronous sigma delta modulator as a preferred means for deriving the square wave, which is duty cycle modulated by the analog input signal. The asynchronous sigma delta modulator mainly comprises an integrating filter and a comparator in feedback arrangement, and is relatively easy to build and robust in operation. The square wave, generated by the asynchronous sigma delta modulator, contains the information in the analog time-positions of its transients. In order to convert the signal into a digital format, the square wave is subsequently sampled by a clock synchronous sampling pulse. The sampling of the square wave results in a digital signal which may be referred to as a one-bit-coded bitstream. It is further disclosed in the above mentioned european patent application that the bitstream may be converted in any suitable PCM-format by means of a decimating digital filter.
The process of sampling the duty cycle modulated square wave implies the introduction of sampling noise whose level is lower the higher the sampling rate is. In practice, when usual moving picture video signals have to be converted, a sufficiently low sampling noise is obtained when the sampling rate, and consequently the communication rate between the sampler and the decimating digital filter, is higher then several Gbits/s. Such a high communication rate may pose a serious problem, for instance when the sampler and the decimating filter have to be implemented on different integrated circuits. However, also when sampler and decimating digital filter are implemented on a single integrated circuit, the transport of the bits between the two functional blocks at this high rate may be impractical. The above mentioned european patent application discloses the use of a polyphase sampler using a plurality of samplers, thereby reducing the sampling rate of each individual sampler. However, this measure does not reduce the total communication rate of the bits originating from the entirety of samplers.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a method of converting an analog input signal into a digital output signal whereby the total communication rate of the digital output signal is substantially reduced with respect to the previously proposed arrangements and the method according to the present invention is characterized in that a clock synchronous subsampling signal, having a predetermined subsampling period, is derived and that said step of sampling the duty cycle modulated square wave includes the step of detecting, within each subsampling period, the position of sampling pulses which approximately coincide with the transients of the duty cycle modulated square wave. Therefore, rather than passing the high rate serial bitstream for further processing, the addresses of the transients of the square wave within a frame of subsampling periods, are passed.
It may be noted that it is known per se to apply so called run-length coding methods, which determine in a bitstream the length of the portions of bits of one value, and which output codes representing these lengths rather than the bitstream itself, thereby also substantially reducing the communication rate of the digital signal. However, these methods have the disadvantage that the codes, representing the run-lengths, are generated at irregular intervals, which make their subsequent decoding more difficult. More particularly, a considerable amount of signal processing with a substantial amount of hardware is required for this approach. In contradistinction therewith, the method of the present invention generates subsampling periods and in each subsampling period the approximate positions of the transients of the duty cycle modulated square wave. In this way an “address coding” of the positions of the transients within each subsampling period is achieved. However, other schemes are possible, e.g. first counting and storing the number of sampling pulses from the start of the subsampling period until the first transient of the duty cycle modulated square wave and then counting and storing the number of sampling pulses from the first transient to the second transient (if any) and eventually from the second transient to the third one and so on. This gives in effect a combination of “address coding” and “run length coding” but without the above mentioned drawback of known “run length coding ”.
In the method of the invention, each subsampling period maximally comprises a predetermined number of square wave transients. This number depends on the frequency (the rate) of the subsampling pulses relative to the frequency of the square wave. When said number is larger, more hardware is required for carrying out the method. On the other hand, when the number is smaller, the reduction of the total communication rate is less. It has been found a good compromise when, according to a further characteristic of the invention the length of the subsampling period is selected so that each subsampling period includes no more than two transients of the duty cycle modulated square wave. Then the position of the first transient may e.g. be stored in a first register and the position of the second transient in a second register. However, it is alternatively possible to store e.g. each leading transient of the square wave in the first register and each trailing transient in the second register, or vice versa.
It may further be noted that the sampling of the square wave may either be direct or indirect. In case of direct sampling the square wave is sampled by a high rate sampling pulse thereby creating a high rate bitstream and subsequently, within each subsampling period, the positions of those bits of the bitstream, which approximately coincide with the transients of the square wave, are detected and stored. In case of indirect sampling no high rate bitstream is created and therefore the hardware required for carrying out the method of the present invention is simpler and more robust. The method with indirect sampling is characterized by counting sampling pulses during each subsampling period and by detecting and storing the value of the count resulting from said counting upon each occurrence of a transient of the duty cycle modulated square wave.
The method of the present invention may not only be used to reduce the total communication rate of the digital signal, but additionally and simultaneously to multiplex a plurality of digital signals originating from a plurality of analog input signals. Therefore the method according to the present invention may be further characterized by simultaneously converting a plurality of analog input signals into a corresponding plurality of digital output signals each thereof comprising information on the position, within each subsampling period, of sampling pulses which approximately coincide with the transients of the duty cycle modulated square wave obtained from the corresponding analog input signal, and by subsequently multiplexing the plurality of digital output signals into a digital multiplex signal for further processing. Preferably the counting of the sampling pulses for the conversion of said plurality of analog input signals is achieved by means of a common counter.
The invention also relates to an arrangement for converting an analog input signal into a digital output signal which is characterized by a duty cycle modulator for deriving a square wave duty cycle modulated by the analog input signal, a clock synchronous sampling pulse gener
Biren Steven R.
Kost Jason L W
U.S. Philips Corporation
Young Brian
LandOfFree
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