Method for controlling time point for data output in...

Details Method for controlling time point for data output in... Method for controlling time point for data output in...

2007-07-09

2008-12-16

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

07466622

ABSTRACT:
Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device. In other words, the time point to generate the internal read command when CAS latency corresponds to 2N+2 (N=0, 1, 2, . . . ) is delayed by 1tCK as compared with the time point to generate the internal read command when CAS latency corresponds to 2N+1, and the 1tCK is a period of an external clock applied to the synchronous memory device.

REFERENCES:
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6212127 (2001-04-01), Funaba et al.
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6449674 (2002-09-01), Yun et al.
patent: 6680866 (2004-01-01), Kajimoto
patent: 6778465 (2004-08-01), Shin
patent: 2004/0109382 (2004-06-01), Chung et al.
patent: 464876 (2001-11-01), None

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