Method for controlling thermal interface gap distance

Details Method for controlling thermal interface gap distance Method for controlling thermal interface gap distance

1999-09-30

2001-09-25

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S108000, C438S118000, C438S122000

Reexamination Certificate

active

06294408

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally directed to structures and methods for controlling the thickness of the gap between an electronic circuit chip and a lid, heat sink, or other cooling mechanism. More particularly, the present invention is directed to a system in which the size of the gap between the circuit chip and the lid or heat sink is controlled and preferably controlled so that this gap is as small as possible without deleteriously affecting the assembly process, chip integrity, or long-term performance. Even more particularly, the present invention is directed to an assembly method and system for controlling the thickness of paste material disposed between a chip and a lid or cover of a single chip or multi-chip module.
BACKGROUND OF THE INVENTION
As device integration levels continue to increase, the demand for a more efficient solution to the cooling of high power electronic circuit chips becomes an even more important ingredient in achieving required system performance. The use of thermal interface material (paste or grease) to cool single chip or multi-chip modules is highly desirable because of its simplicity and high thermal performance. Thermal interface materials are also not impacted by small particle contamination; hence, module assembly can be done in non-clean room environments, which is a factor in helping to reduce module assembly costs. Furthermore, module assembly can be done without demanding cooling schemes that use parts such as springs and pistons which may be sensitive to particle contamination. Further still, the compliance of thermal interface materials allows them to absorb mechanical tolerances which are associated with chip height and hardware variations.
It is desirable for electronic devices to operate at low temperatures for enhanced performance and reliability. This is particularly true for complimentary metal oxide semiconductor (CMOS) devices for which a reduction in temperature produces a gain in system speed. To a first order of approximation, the temperature of a flip chip is given by the following one-dimensional heat conduction equation:
T
chip
=T
air
+P
chip×R
int
+P
mod
×R
ext
In the case of a single chip module, the module power equals the chip power, and the above equation simplifies to:
T
chip
=T
air
+P
chip
×(R
int
+R
ext
)
In the above equations, R
int
represents the internal thermal resistance of the module: the resistance from the chip, through the thermal interface material, to the module lid. F
ext
represents the thermal resistance external to the module: the lid-to-heat sink interface plus the heat sink resistance, including air heating effects.
The internal thermal resistance is composed of three resistances in series:
R
int
=R
chip
+R
interface material
+R
lid
Because the lid is typically made of a high thermal conductivity material, such as aluminum, the thermal interface material resistance, which includes the interface resistance between the chip and interface material and between the interface material and lid, is the largest contributor to the internal thermal resistance, R
int
. Reduction of the thermal interface material resistance is a significant factor, therefore, in reducing the overall device temperature.
The thermal resistance of the interface material is given by the following equation:
 R
interface material
=L
gap
/(K
interface material
×A
chip
×C)+R
interface
where L
gap
is the thickness of the interface material between the chip and the module lid, K
interface material
is the interface material thermal conductivity, A
chip
is the area of the chip, and C is the percentage of the chip covered by the interface material. It is clear from this expression that, for constant chip size and coverage, reduction of the interface material thermal resistance, R
interface material
, can be accomplished by (i) reduction of the interface material gap size, (ii) an increase in the thermal conductivity of the thermal interface material, or (iii) both.
Current designs rely on the compliance of the thermal interface material to accommodate variations in the thermal interface material gap arising due to hardware and chip height tolerances. The statistical variations of these tolerances are typically at least ±0.076 mm (±0.003 inches). Typical nominal gaps are 0.178 to 0.305 mm (0.007 to 0.012 inches). When high thermal conductivity interface materials are used, a large force is required to squeeze the interface material into even smaller gaps because high thermal conductivity interface materials typically have high solids loading and hence high viscosity. As a result, gaps of 0.178 mm (0.007 inches) or greater have been used.
Current methods for joining a substrate having a chip mounted upon it, and a lid to form a module, include a curing process. When the curing process is used to seal an encapsulated structure, the pressure that builds up within the module may create seal defects. In addition, seal defects can result when the curing process is also relied upon to compress the thermal interface material thickness to a thickness equal to the desired gap thickness.
To overcome the shortcomings of the current methods, a new structure and method are provided for controlling the gap between a chip and a module lid. An object of the present invention is to control the gap between the chip and a module lid while maintaining the chip and its interconnect structure within a sealed (hermetic or non-hermetic) environment. The sealed package is desirable to prevent moisture from contacting the chip and to maintain the interface material performance over long periods of time. Accordingly, the improved use of thermal interface material cooling, as incorporated in the present invention, becomes more efficient. It is another object of the present invention to provide a method for assembling a sealed module as described above, without the associated problems of internal pressure buildup or other sealing defects.
It is yet another object of the present invention to provide a method and apparatus for controlling the thickness of compliant thermally conductive material disposed between a chip and a lid in either a single chip or multi-chip module. Another object of the present invention is to improve the flow of heat away from an integrated circuit chip device. A related object of the present invention is to decrease operating temperatures, which increases the operating speed of electronic circuit chip devices and improves reliability. It is a still further object of the present invention to extend the performance range of thermal interface material cooling systems. It is also an object of the present invention to reduce the statistical variations in interface material gap tolerance in assembled electronic circuit chip modules.
A more specific object of the present invention is to reduce the gap between a thermally conductive lid and an electronic circuit chip which is encapsulated by the lid to a distance of 0.152 mm (0.006 inches) or less. Another object of the invention is to decrease seal defects and to increase assembly yield. It is still another object of the present invention to not only reduce but to also control the thickness of thermal interface materials disposed between electronic circuit chips and the packages which contain them.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides, in a preferred embodiment, an electronic flip chip assembly with controlled thermal interface material thickness. In particular, a substrate having electrical conductors is provided together with an electronic circuit chip which is affixed to the substrate so as to make electrical contact between the circuit chip and electrical conductors on the substrate. A thermal interface material is disposed on an upper side of the circuit chip. A substantially flat thermally conductive lid is disposed over the chip and in thermal contact with the interfac

Affiliated with

Also associated with

Rating

Method for controlling thermal interface gap distance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling thermal interface gap distance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling thermal interface gap distance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2502107