Method for controlling the thickness of a passivation layer on a

Details Method for controlling the thickness of a passivation layer on a Method for controlling the thickness of a passivation layer on a

1999-03-25

2000-08-01

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

438128, 438132, H01L 2182

Patent

active

060965797

ABSTRACT:
A method for controlling the thickness of a passivation layer underlying with a fuse on a semiconductor device is disclosed herein. The anti-reflective coating on a metal layer is buried in the passivation layer, and the fuse is in a semiconductor device. The method includes the following steps. First, use a first etchant and Ar to etch the passivation layer till the anti-reflective coating is exposed, the first thickness of the passivation layer above the anti-reflective coating is smaller than the second thickness of the passivation layer above the fuse. Then, utilize a second etchant to etch the anti-reflective coating till the metal layer is exposed. The second etchant has a selectivity ratio from the anti-reflective coating to the passivation layer being at least 10. The second etchant mentioned above includes BCl.sub.3, Cl.sub.2, O.sub.2, and Ar.

REFERENCES:
patent: 5223080 (1993-06-01), Ohta et al.
patent: 5578517 (1996-11-01), Yoo et al.
patent: 5753539 (1998-05-01), Okazaki
patent: 5930664 (1999-07-01), Hsu et al.

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