Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
1999-10-27
2001-12-25
Wong, Edna (Department: 1741)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C428S620000, C428S469000, C205S157000, C205S182000, C205S220000
Reexamination Certificate
active
06333120
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates to a method for electroplating copper onto a substrate, and more particularly, to a method that results in a copper layer having a substantially random texture. The texture and microstructure of the copper layer is not dependent upon the underlayer metal. The present invention also relates to the coated structure obtained by the process of the present invention.
2. Background of Invention
On VLSI and ULSI semiconductor chips, Al, alloys of AlCu and related alloys are used for conventional chip wiring materials. More recently Cu and alloys of Cu have been suggested as chip wiring material. The use of Cu and Cu alloys results in improved chip performance and superior reliability when compared to Al and alloys of Al.
Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of AlCu; thus narrower lines can be used and higher wiring densities will be realized.
The advantages of Cu metallization have been recognized by the entire semi-conductor industry. Copper metallization has been the subject of extensive research as documented by two entire issues of the Materials Research Society (MRS) Bulletin, one dedicated to academic research on this subject in MRS Bulletin, Volume XVIII, No. 6 (June 1993) and the other dedicated to industrial research in MRS Bulletin, Volume XIX, No. 8 (August 1994). A 1993 paper by Luther et al.,
Planar Copper
-
Polyimide Back End of the Line Interconnections for ULSI Devices
, in PROC. IEEE VLSI MULTILEVEL INTERCONNECTIONS CONF., Santa Clara, Calif., Jun. 8-9, 1993, p. 15, describes the fabrication of Cu chip interconnections with four levels of metallization.
Processes such as Chemical Vapor Deposition (CVD) and electroless plating are popular methods for depositing Cu. Both methods of deposition normally produce at best conformal deposits and inevitably lead to defects (voids or seams) in wiring especially when trenches have a cross section wider at the top than at the bottom as a result of lithographic or reactive ion etching (RIE) imperfections. Other problems of CVD have been described by Li et al.,
Copper
-
Based Metallization in ULSI Structures—Part II: Is Cu Ahead of its Time as an On
-
chip Material?, MRS BULL., XIX,
15 (1994). In electroless plating, while offering the advantage of low cost, the evolution of hydrogen during metal deposition leads to blistering and other defects that are viewed as weaknesses for industry wide implementation.
More recently, improved methods for electroplating copper have been provided such as that disclosed in U.S. application Ser. No. 08/768,107 to Andricacos et al, entitled “Electroplated Interconnection Structures on Integrated Circuit Chips”, filed Dec. 16, 1990, now abandoned, and assigned to International Business Machines Corporation, the assignee of the present application, disclosure of which is incorporated herein by reference. The process disclosed therein provide a method for fabricating a low cost, highly reliable Cu interconnect structure for wiring in integrated circuit chips with void-free seamless conductors of sub-micron dimensions.
When plating, the texture and microstructure of the plated metal is essentially controlled by the nature of the seed layer below. As a consequence of this phenomenon, the microstructure and texture of a plated film is often identical or close to that of the underlying substrate. For example, the texture of electroplated copper thin films for interconnect applications tends to be highly oriented with a <111> texture. This high <111> texture in the plated film being inherited from the highly oriented sputtered seedlayer beneath the plated film.
However, for copper interconnection technology, the present inventors have discovered that copper films with random orientation possess high electromigration lifetimes. In general, it has been found according to the present invention that copper films with random or near random texture to be superior to highly oriented copper films deposited by either PVD or CVD methods. Since the plated Cu film grows somewhat epitaxially on the seed layer, the plated Cu film tends to be also <111> textured. The plated Cu texture is difficult to modify or to control once it has developed and it is difficult to decouple the texture of the plated Cu film from that of the original Cu seed layer.
However, in practice, it is difficult to realize random texture in electroplated copper films, for the reasons given above. As a consequence, there exists the need for methods that can decouple the texture of electrodeposited metal from the texture of the seed layer or substrate underlying the plated film.
SUMMARY OF INVENTION
The present invention provides a process and structure that decouples the texture of a deposited metal from the texture of the substrate below the deposited film. The structure and process for electrodepositing copper according to the present invention is such that the texture of the plated film is independent of the texture of the seed layer or nature of the substrate below. The process of the present invention provides electroplated copper films exhibiting random or near random texture, as opposed to the nominal and routine highly oriented films.
In particular, the plating method of the present invention comprises plating a layer of copper onto a substrate up to a maximum thickness of about 350 nanometers, followed by subjecting the copper coated substrate to an oxygen-containing gaseous ambient for a time sufficient to roughen the surface of the plated copper. Copper is then electroplated onto the roughened copper surface to provide the desired copper thickness.
The present invention also relates to a copper plated substrate obtained by the above disclosed process.
A still further aspect of the present invention relates to a copper plated substrate which comprises a substrate comprising a first copper underlayer having a maximum thickness of up to 350 nanometers, and a second layer of copper on the copper underlayer wherein the second layer of copper has a thickness of at least about 200 nanometers and a substantially random texture. For purposes of definition, substantially random texture in copper is determined by a diffraction scan of the copper using a conventional (Bragg-Brentano optics) x-ray powder diffractometer. From the diffraction scan, the peak intensities of the Cu<111> and Cu<200> reflections are obtained. If the ratio of the Cu<200> to Cu<1111> peak intensity is greater than {fraction (15/100)}, then the copper is considered to have substantially random texture.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5366814 (1994-11-01), Yamanishi et al.
patent: 6114097 (2000-09-01), Malba et al.
patent: 6123825 (2000-09-01), Uzoh et al.
patent: 6180505 (2001-01-01), Uzoh
Ritzdorf et al, Self-Annealing of Electrochemically Deposited Copper Films in Advanced Interconnect Applications, IITC 98, 1998, pp. 166-168. No Month Available.
Harper et al, Mechanisms for Microstructure Evolution in Electroplated Copper Thin Films near Room Temperature, Journal of Applied Physics, vol. 86, No. 5, Sep. 1, 1999, pp. 2516-2525.
Cabral, Jr. et al, Room Temperature Evolution of Microstructure and Resistivity in Electroplated Copper Films, Conference Proceedings ULSI XIV, 1999, pp. 81-87. No Month Available.
DeHaven Patrick William
Locke Peter S.
Rodbell Kenneth P
Uzoh Cyprian Emeka
Connolly Bove Lodge & Hutz
International Business Machines - Corporation
Trepp Robert M.
Wong Edna
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