Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating resistive material
Reexamination Certificate
2001-02-26
2002-11-05
Powell, William A. (Department: 1765)
Etching a substrate: processes
Forming or treating electrical conductor article
Forming or treating resistive material
C216S013000, C216S059000, C216S075000, C216S084000, C216S100000, C438S008000, C438S742000, C438S754000
Reexamination Certificate
active
06475400
ABSTRACT:
TECHNICAL FIELD
A method for producing thin film resistors to a tighter sheet resistance specification.
BACKGROUND AND SUMMARY
Thin film resistors are used in most GaAs and InP devices and integrated circuit fabrication processes, in thin-film substrate manufacturing, and in some Si processes. The resistor sheet resistance typically has a specified tolerance of ±15%, although with special care in fabricating the thin film resistors, the resistor sheet can be controlled to ±10%. However, for many integrated circuit designs it would be of a great advantage to be able to control the sheet resistance to a much tighter tolerance. This is especially true in very high speed integrated circuits where resistor values need to be controlled well in impedance matching circuitry.
One method of achieving tight control of the resistor sheet resistance is to re-process any thin film that does not have the desired sheet resistance by stripping the thin film and re-depositing it. However, such a procedure essentially doubles the cost of processing the thin film resistor. Therefore, a need exists for inexpensively controlling the sheet resistance of thin film resistors to within a tight tolerance of their targeted value.
The present invention addresses this need. More particularly, a disclosed method of the invention improves the tolerance of thin film resistors to within ±3% or better with minimum additional processing expense. To this end, the disclosed method for controlling the sheet resistance of thin film resistors comprises determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate. The thin film resistor material is deposited on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance for the deposited thin film resistor material within a first specified tolerance. The thin film resistor material is deposited by the deposition process to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance. A small amount of material is then removed from the surface of the deposited thin film resistor material by an etching or ion bombardment process to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the etching or ion bombardment process, where the second specified tolerance is less than the first specified tolerance. The etching process employed in a preferred embodiment uniformly removes material from the surface of the deposited thin film resistor by argon sputter etching.
According to the disclosed, preferred embodiment, the method further comprises, after the thin film resistor deposition, measuring the sheet resistance of the deposited thin film resistor material by measurement or calculation, determining the thickness of the deposited thin film resistor material, calculating the thickness of the deposited thin film resistor material needed to be removed to raise the sheet resistance to the desired final value, and calculating the time for performing the removing process to remove the calculated thickness needed to be removed based on a measured removal rate for the removing process. Further, the method includes patterning a thin film resistor from the thin film resistor material on the substrate. The patterning can be performed before or after the sheet resistance is raised to the desired final value. The invention advantageously permits the thin film resistor sheet resistance on critical integrated circuit designs to be controlled to better than ±3% with minimum additional processing expense.
These and other objects, features and advantages of the present invention will become more apparent from the following description of a preferred embodiment of the invention.
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“In Situ-Trimmed Fine-Grained Polysilicon Resistors,” IBM Technical Disclosure Bulletin, vol. 33, No. 5, pp. 280-281, Oct. 1990.
Antonelli Terry Stout & Kraus LLP
Powell William A.
TRW Inc.
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