Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
2002-06-19
2004-08-24
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S022000
Reexamination Certificate
active
06780552
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for controlling the quality of a lithographic structuring step performed in an exposure tool for structuring a pattern into a photoresist layer of a semiconductor wafer. The quality is represented by a group of at least two quality parameters measured in at least one metrology tool.
Semiconductor wafers commonly experience multiple exposure steps followed by other processing steps like etching, polishing, etc. in order to be finally structured with one or more integrated circuits. Due to the steadily increasing customer specifications that have to be fulfilled, the quality performance of each exposure step is controlled by a set of metrology measurements.
The quality of an exposure step can be represented by a group of quality parameters like the critical dimension, the overlay accuracy from layer to layer, the layer thickness, the absolute position accuracy (registration), etc. The strength of the requirements to be fulfilled by an integrated circuit, i.e. a wafer, typically depend on the layer that is actually being structured. For example, some layers are structured with dense patterns, such that narrow tolerance ranges for the critical dimension exist. In other cases, two subsequent layers, one being structured above the other, require a minute adjustment to each other to provide contacts having a minimum cross-section in order to guarantee an accurate working function of the integrated circuit.
A set of tolerance specifications for the quality parameters are commonly deduced from the design rules and the layer architecture combined with current technology feasibilities. The specifications are generally provided prior to starting mass production of the wafers in a fabrication facility. That is, each of the metrology tools that measures at least one of the quality parameters is connected to a product database containing the pattern design files. The quality check, i.e. the comparison whether the just measured quality parameter is within the prescribed tolerance range for that parameter, is performed either on the metrology tool after having received the tolerance specification information, or after transferring its measured values to the MES-system (manufacturing execution system), which performs electronic data collection.
Unfortunately, the amount of rework is growing with the advent of tighter tolerance specifications introduced with advanced technologies. This is because when the measured values of a wafer do not fulfill the specified tolerances, the wafer must be reworked, i.e. the resist has to be stripped off, and a new coating step has to be performed after which the wafer is re-exposed. This disadvantageously increases the costs in material and tool time and also results in a loss in yield. A remedy would be to decrease the strength of tolerance specifications, but this will lead to a disadvantageous loss in competitiveness to other manufacturers.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for controlling the quality of a lithographic structuring step which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the invention to reduce the amount of rework, thereby decreasing the costs related to exposing a semiconductor wafer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for controlling quality of a lithographic structuring step performed in a lithographic structuring tool for structuring a pattern into a layer of a plate-like object. The method which includes steps of: representing the quality by a group of at least two quality parameters including a first quality parameter representing a property of the pattern and a second quality parameter representing a property of the pattern being different than the property represented by the first quality parameter; measuring the first quality parameter in a first metrology tool; providing at least one value of the first quality parameter; calculating a width of a tolerance range for the second quality parameter in response to providing the at least one value of the first quality parameter; providing the plate-like object to the second metrology tool; measuring the second quality parameter in a second metrology tool; and comparing the second quality parameter with the width of the tolerance range that has been calculated.
The method is particularly advantageous in the case when the plate-like object is a semiconductor device, e.g. a semiconductor wafer, and the lithographic tool is an exposure tool, for example, a wafer scanner or stepper, or an x-ray, EUV−, ion or electron beam projection tool. An etching tool can be also used as a structuring tool to apply the inventive process window handling method.
The plate-like object can be any object, which can be structured on its surface, e.g. a mask or reticle, or a flat panel display.
According to the present method, the quality parameters are measured subsequently in one, two, three, or more metrology tools after the exposure of a semiconductor wafer are checked for validity in dependence from the respective other measurement results. This means that the measurement result of a first measured quality parameter has an influence on the tolerance specification for the second or any further quality parameter being measured afterwards, or even prior to the current measurement, when the validity check of the first quality parameter is taken a posteriori.
In the prior art, each quality parameter, such as the critical dimension, the overlay accuracy, the layer thickness, the position accuracy, or the alignment parameters, for example, grid scaling, magnification, rotation, etc.—the latter ones being derived, e.g., in overlay metrology tools—are each compared against a specific tolerance range specified in advance of the begging of the wafer production. Instead of using these rigidly set tolerance ranges, the present method provides a flexible use of ranges, which utilizes advantageous conditions. This is fulfilled by a first measured quality parameter, used to adjust the tolerance range, which is applied to the validity check of the second measured quality parameter.
The advantage of the present method is obtained from the physical or geometrical interdependence of the metrology or quality parameters involved. A specific value measured for one parameter can have a direct influence on the degree of freedom of another parameter. For example, an increased value of the critical dimension of a structure might increase a tolerance range width of an overlay accuracy for a contact hole to which it should be connected, or vice-versa, decreases the tolerance range width for a structure that is to be placed directly beside the first structure, if they are not supposed to be connected. Therefore, data of actually structured patterns—perhaps in combination with design data—are used as inputs to derive tolerance range widths instead of using design data only.
Since the dynamic determination of the tolerance range width of the second quality parameter allows an adaptation of the quality check to the current and actual requirements of the design patterns on the wafer under investigation, the dynamic tolerance range widths will generally be larger than those specified rigidly according to prior art. In particular, the process window in a quality parameter plane can be extended into regions, where the functionality of the integrated circuit can still be warranted depending on the specific combination of values for the first and second quality parameter. Thus, rework is advantageously reduced, thereby decreasing costs needed for material and machines.
The inventive method works with any sequence of measuring quality parameters. Typically, semiconductor wafers will be taken from the lithography track after exposure and the overlay control is measured first, followed by a critical dimension measurement, or vice versa. Then, the wa
Schedel Thorsten
Schmidt Sebastian
Zimmermann Jens
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Young Christopher G.
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