Method for controlling silicon etch depth

Details Method for controlling silicon etch depth Method for controlling silicon etch depth

1992-06-26

1995-03-07

Fourson, George

Fishing, trapping, and vermin destroying

156626, H01L 21302

Patent

active

053957695

ABSTRACT:
The present invention is a structure and method for controlling the depth of an etching process. In particular, the method and structure of the present invention creates a marker layer which resides between a layer to be etched and a protected layer. The marker layer is detected during the etch process and the etch process is controlled based on the detection of the marker layer. The marker layer has physical characteristics which are very similar to the layers being etched or protected. The marker layer has a similar lattice constant and electrical behavior to either the etched layer or the protected layer. The marker layer has very different optical properties from the etched or protected layers so that even a thin marker layer can be easily detected using in-situ ellipsometric measurements. A specific embodiment of the present invention is a layer of SiGe interposed between a thick silicon layer and a thin silicon layer. In particular, the SiGe layer has a composition of approximately 10% of germanium and has a thickness of approximately 10.ANG.. The thick silicon layer has a thickness of approximately 5,000.ANG. and the thin silicon layer has a thickness of approximately 1,000.ANG.. A method of etching the thick silicon layer, incorporating one embodiment of the present invention, is to perform a RIE process on the thick silicon layer while monitoring the RIE process with an ellipsometer. When the RIE process encounters the underlying marker layer, the ellipsometer measurements show a marked change. The marked change in the ellipsometer measurements indicate when to stop the RIE process. When the marker layer is very thin, such as 10.ANG., the RIE process is stopped immediately and the underlying thin silicon layer is not etched into. Even though the RIE process is not uniform, and parts of the marker layer will remain on the surface of the protected layer, this will not affect the electrical behavior of the resulting semiconductor device using this process. This is because the thin SiGe marker layer has electrical characteristics which are very similar to the underlying silicon layer.

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