Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2002-11-07
2003-11-11
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S099000, C700S100000, C700S101000, C700S102000, C700S103000
Reexamination Certificate
active
06647307
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a system and method for operating a manufacturing line, and more particularly to a system and method for controlling queue time constraints in a fabrication facility.
BACKGROUND
A typical process in manufacturing the semiconductor integrated circuit requires hundreds of steps. These steps include several kinds of stages such as diffusion, lithography, etching, ion implantation, deposition and sputtering. In these kinds of stages, diffusion and implantation generally require longer processing time than other process stages. Other processes will require less processing time. In addition, some processes, e.g., those with long processing time, can be simultaneously performed on several wafer lots (commonly referred to as a “batch”).
In a semiconductor's processing line, several lots (and/or batches) and many kinds of products are put into the processing line continuously at the same time. Thus, many kinds of products are operated on during different kinds of stages in the processing flow. But since the processing time of each product is different from each other, determining how many and which wafers to be dispatched into a stage of the processing flow is a dispatching problem.
As another consideration, some processes must be performed within a certain amount of time after other processes. For example, after a deposition step a semiconductor wafer can be exposed to air for only a limited amount of time before the quality of the deposited film will begin to degrade. The time between processes can be referred to as the queue time. Limits on this time can be referred to as queue time constraints.
To control the operation of a fabrication plant, manufacturers have utilized queuing theory, which deals with problems that involve queuing or waiting. These theories can be utilized to optimize the flow of devices, or lots that include a number of devices, through a fabrication facility. For example, Little's formula can be used to calculate expected time between processes. This formula states that the mean number of jobs in a queuing system in the steady state is equal to the product of the arrival rate and the mean response time.
To ensure high quality, controls can be utilized to limit the queue time of wafers in progress after certain processes. This can be especially important for processes that are sensitive to time. If the queue time of a lot is not well controlled, the yield quality can be seriously impacted. For example, wafers may need to be scrapped if the film quality is damaged by exposure to air.
Some lots may be forced to wait beyond the desired queue time due to insufficient capacity, for example when too many wafers are awaiting the same tool. To minimize this occurrence, a safety WIP (work in process) can be designed to control the dispatch problem within a queue time constraint. The safety WIP is used to control the queue WIP level so that the capacity demand for the WIP level does not exceed the current capacity. The current methods, however, are insufficient to meet the increasing demands of modern fabrication facilities.
SUMMARY OF THE INVENTION
The present invention includes embodiments that overcome several of the disadvantages found in the prior art. In one aspect, a multiple processing demand time (MPDT) formula is defined using Little's formula. A smart algorithm controls the lot dispatching for queue time constraints. For a given processing tool with multiple queue time constraints, the lot-dispatching control logic procedure at the tool can utilize an algorithm to systematically control the number of lots dispatched to any given tool.
In the preferred embodiment, the algorithm can be performed using the following steps. The queue time constraint tolerances and tool throughput are initialized for each product. Next the multiple processing demand time can be calculated for each product. The aggregating queue time constraint can then be calculated for each product. If the multiple processing demand time is less than the aggregating queue time constraint for each queue time limit tool, then any lot can be selected to be processed. Otherwise, the product at the given tool should be further processed.
As a specific example, aspects of the present invention can be used to fabricate a semiconductor device. In this process, the semiconductor device is processed at a first tool. A mean processing demand time can be calculated for the semiconductor device at a second tool and a queue time constraint tolerance can be calculated for the semiconductor device between the second tool and a third tool. The semiconductor device can then be dispatched to the second tool if the mean processing demand time is less than the queue time constraint. The semiconductor device can then be processed at the second tool and at the third tool.
Various aspects of the present invention have advantages over previously used methods. For example, the preferred embodiment approach has better control capability for lot scheduling and dispatching than the safety WIP approach. Also, the preferred embodiment approach can be easily utilized to control queue time constraints for complex multiple products. The preferred embodiment approach can also effectively solve the problems associated with single and multiple queue time constraints.
REFERENCES:
patent: 5544350 (1996-08-01), Hung et al.
patent: 5546326 (1996-08-01), Tai et al.
patent: 5586021 (1996-12-01), Fargher et al.
patent: 5612886 (1997-03-01), Weng
patent: 5751580 (1998-05-01), Chi
patent: 5818716 (1998-10-01), Chin et al.
patent: 5825650 (1998-10-01), Wang
patent: 5841677 (1998-11-01), Yang et al.
patent: 5880960 (1999-03-01), Lin et al.
patent: 5928389 (1999-07-01), Jevtic
patent: 6263253 (2001-07-01), Yang et al.
patent: 6353769 (2002-03-01), Lin
patent: 6356797 (2002-03-01), Hsieh et al.
patent: 6415260 (2002-07-01), Yang et al.
patent: 6434443 (2002-08-01), Lin
patent: 6463346 (2002-10-01), Flockhart et al.
patent: 6480756 (2002-11-01), Luh et al.
Hsu Kuang-Huan
Huang Liang-Kai
Lu Span
You Ren-Chyi
Jarrett Ryan
Picard Leo
Slater & Matsil L.L.P.
Taiwan Semiconductor Mfg. Co. Ltd.
LandOfFree
Method for controlling queue time constraints in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for controlling queue time constraints in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling queue time constraints in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3116169