Method for controlling power and slew in a programmable logic de

Details Method for controlling power and slew in a programmable logic de Method for controlling power and slew in a programmable logic de

1997-08-21

2000-03-14

Teska, Kevin J.

39550003, 39550007, 39550018, G06F 1750

Patent

active

060383860

ABSTRACT:
A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths. Also, a second sub-group of the resources is identified which, when operated in a slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of all paths ending at that output terminal. A target PLD is then programmed in accordance with the placement arrangement, and the resources of the first and second groups are set to low power mode and slow slew mode, respectively.

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