Static information storage and retrieval – Addressing – Sync/clocking
Utility Patent
1997-05-21
2001-01-02
Nelms, David C. (Department: 2511)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189011, C365S189050, C365S189080
Utility Patent
active
06169703
ABSTRACT:
This disclosure involves controlling electronic high speed memory devices while running them as fast as possible, and maximizing memory bandwidth and utilization.
Some Salient Themes Hereof Are
Maximizing the operating speed (and bandwidth) of a high speed memory unit (e.g. static RAM), as initiated by a compatible high-frequency clock source, using a bi-stable stage for in-storage (or timing coordinator) of input address, data and Rd/Wr commands (pref. a flip-flop for each of these three), with data-out on a data bus (pref. same as data-in bus, coupled to data-in flip flop) and arranged to be in “perpetual read-enable” state except during write operations.
The data-out bus preferably feeds a bi-stable out-store buffer, also controlled by the clock and a read-flip-flop, which is coupled to the memory (Read input) via Inverter means.
Thus, an object hereof is to address and resolve at least some of these problems and provide at least some of the here-described features.
Other objects and advantages of the present invention will be apparent to those skilled in the art.
REFERENCES:
patent: 5680591 (1997-10-01), Kansal et al.
McCormack J.
Nelms David C.
Phan Trong
Starr Mark
Unisys Corp.
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