Method for controlling electrical breakdown in semiconductor pow

Details Method for controlling electrical breakdown in semiconductor pow Method for controlling electrical breakdown in semiconductor pow

1993-03-12

1995-07-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG13, 148DIG126, 148DIG151, H01L 21265

Patent

active

054340950

ABSTRACT:
A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

REFERENCES:
patent: 3458781 (1989-07-01), Simon
patent: 3600647 (1971-08-01), Gray
patent: 4101922 (1978-07-01), Tihanyi et al.
patent: 4366495 (1982-12-01), Goodman et al.
patent: 4376286 (1983-08-01), Lidow et al.
patent: 4416708 (1983-11-01), Abdoulin et al.
patent: 4499652 (1985-02-01), Shrivastava
patent: 4596068 (1986-06-01), Peters, Jr.
patent: 4599118 (1986-07-01), Han et al.
patent: 4601096 (1986-07-01), Calviello
patent: 4656492 (1987-04-01), Sunami et al.
patent: 4766094 (1988-08-01), Hollinger
patent: 5015596 (1991-05-01), Toyoda et al.
patent: 5185279 (1993-02-01), Ushiku

Affiliated with

Also associated with

Rating

Method for controlling electrical breakdown in semiconductor pow does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling electrical breakdown in semiconductor pow, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling electrical breakdown in semiconductor pow will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2418902