Method for controlling delay time of signal in semiconductor...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S1540PB

Reexamination Certificate

active

06842033

ABSTRACT:
A method for controlling a delay time of a signal in a semiconductor device is disclosed, which comprises the steps of: a) applying a test mode pulse signal; b) generating N number of test mode selection signals which are synchronized with the falling edges of the test mode pulse signal to respond sequentially; c) sequentially regenerating the (N−1)th test mode selection signal after the Nth test mode selection signal is generated; and d) repeating step c, wherein an input signal inputted to the semiconductor device is delayed by a predetermined time to be outputted as an output signal only when first to the (N−1)th test mode selection signals are enabled, and the delayed times are different from each other according to the first to the (N−1)th test mode selection signals. In the method, delay degree of a predetermined signal can be freely adjusted in a test mode. Further, a desired delay degree can be set by means of an external signal, regardless of the number of unit delay devices constituting a delay circuit.

REFERENCES:
patent: 4497056 (1985-01-01), Sugamori
patent: 4929888 (1990-05-01), Yoshida
patent: 5894226 (1999-04-01), Koyama
patent: 6158030 (2000-12-01), Reichle et at.

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