Method for controlling data output timing of memory device...

Details Method for controlling data output timing of memory device... Method for controlling data output timing of memory device...

2008-07-01

2008-07-01

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S233120, C365S194000

Reexamination Certificate

active

07394722

ABSTRACT:
Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS latency, wherein the CAS latency control unit generates a signal for controlling the output driver by using time difference between the DLL clock signal and an external clock applied to the memory device from an exterior.

REFERENCES:
patent: 6330200 (2001-12-01), Ooishi

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