Method for controlling clock cycle time for reduced power...

Details Method for controlling clock cycle time for reduced power... Method for controlling clock cycle time for reduced power...

2011-03-01

2011-03-01

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233130, C365S233100, C365S194000, C365S189070, C365S230020, C365S227000, C327S149000, C327S153000, C327S158000, C327S156000, C327S161000

Reexamination Certificate

active

07898901

ABSTRACT:
Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

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