Method for controlling an analog/digital converter

Details Method for controlling an analog/digital converter Method for controlling an analog/digital converter

1999-01-12

2001-01-30

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06181269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for controlling an analog/digital converter (hereinafter called A/D converter), specifically, an A/D converter formed as a semiconductor integrated circuit on a semiconductor substrate.
2. Description of the Prior Art
FIG. 38
shows a block diagram of a successive approximation type A/D converter controlled by a conventional control method, which is disclosed, for example, in Japanese Patent Application JP A 1-321728.
The reference numeral
1
denotes a capacitor,
2
is an inverter. The capacitor
1
and the inverter
2
form a chopper type comparator.
3
is a successive approximation register for storing outputs of the comparator, the output of the comparator is called COMP hereinafter. Reference numeral
4
denotes ladder resistors connected in series.
5
,
6
on both end of the ladder resistors are input terminals for imposing a standard voltage, which corresponds to the maximum input voltage that the A/D converter can convert. A switch group
7
selects a reference voltage VREF from the divided voltages by the ladder resistors
4
, corresponding to the output data of the successive approximation register
3
. The ladder resistors
4
and the switch group
7
form a digital/analog converter for converting the digital output of the successive approximation register
3
to an analog voltage signal. Reference numeral
8
denotes an input terminal for inputting an input voltage VIN.
Reference numerals
9
,
10
,
11
denote semiconductor switches, respectively. The reference voltage VREF output by the switch group
7
is imposed to the capacitor
1
through a semiconductor switch
9
. The input voltage VIN inputted from the input terminal
8
is imposed to the capacitor
1
through a semiconductor switch
10
. The input side and the output side of the inverter
2
are electrically connected or cut off by a semiconductor switch
11
.
Reference numeral
12
is an A/D clock generating block, which generates timing clock signals (hereinafter called signals TZ) for controlling the timing of the turning-on and turning-off of the semiconductor switches
9
-
11
, and the timing of the signal delivery from the successive approximation register
3
to the switch group
7
. The A/D clock generating block is not explicitly referred in JP A 1-321728.
The control of the A/D converter is explained below.
FIG. 39
shows a timing chart of the signals in the A/D converter shown in
FIG. 38
, which is controlled by a conventional method for controlling an A/D converter. In this case, the input voltage VIN inputted from the input terminal
8
is 0.3125 times of the standard voltage, and is converted to a four bit digital signal. In the following explanation, the standard voltage is assumed to be one volt.
At first, a timing signal from the A/D clock generating block
12
makes the semiconductor switch
9
turn off. At the moment when the signal TZ sent from the A/D clock generating block
12
to the successive approximation register
3
changes to HIGH level (hereinafter simply referred “H” or “1”), the digital data stored in the successive approximation register
3
is sent to the switch group
7
. The register
3
is designed so that the first output is always a hexadecimal “8h” signal. The output signal controls the switch group
7
to select a switch to output a half of the standard voltage V, because “8h” in the hexadecimal is a half of “16h”. As a result, the switch group
7
outputs a reference voltage VREF of 0.5 volts.
Next, the A/D clock generating block
12
sends a signal to turn on the semiconductor switch
11
, so that voltages of the input side and output side of the inverter
2
become equal. The value of the equal voltage is determined by the input and output characteristics of the inverter
2
. Next, the semiconductor switch
10
is turned on so that the input voltage VIN charges the capacitor
1
. After charging the capacitor, the semiconductor switches
10
and
11
are turned off successively. When the signal TZ becomes LOW level (hereinafter simply referred to as “L” or “0”), the semiconductor switch
9
is turned on. While the semiconductor switch
9
is on, the reference voltage VREF is imposed to the capacitor
1
through the switch group
7
, and the reference voltage VREF and the input voltage VIN are compared to each other.
When the input voltage VIN is larger than the reference voltage VREF, the inverter
2
outputs “0”, and when the input voltage VIN is smaller than the reference voltage VREF, the inverter
2
outputs “1”. In this case the input voltage VIN is 0.3125V, and the reference voltage VREF is ½ V, thus the output signal COMP of the inverter
2
is “0”, which is sent to the successive approximation register
3
and is stored in its register. Namely the value of the most upper bit is identified to be “0”.
Then, the timing signal from the A/D clock generating block
12
controls the semiconductor switch
9
to turn off again. When the signal TZ becomes “H”, the digital data stored in the successive approximation register
3
is sent to the switch group
7
. As a result, since VIN<0.5 Volts, the switch group
7
selects ¼ volts, which is one fourth of the standard voltage, as a reference voltage VREF, from the outputs of the ladder resistors
7
, corresponding to the digital signal. Next, the semiconductor switch
11
is controlled to turn on so that the input and output sides of the inverter
2
are electrically connected. Then the semiconductor switch
11
is made turn on to charge the capacitor
1
.
After that, the semiconductor switch
9
is turned on and the reference voltage VREF is imposed from the switch group
7
to the capacitor
1
. Then the reference voltage is compared with the input voltage VIN. In this case, the input voltage VIN is 0.3125 volt, and the reference voltage VREF is ¼ volt, namely the input voltage VIN is larger than the reference voltage VREF, thus the output COMP of the inverter
1
is “1”, which is sent to the successive approximation register
3
to be stored therein. The value of the second bit is determined to be “1”in this procedure.
The similar procedures are repeated for the identifying lower bits. The input voltage VIN (0.3125 volt) is successively compared with the reference voltage VREF, which is ⅜ (={fraction (0/2)}+¼+⅛) volts in the third procedure and is {fraction (5/16)} (={fraction (0/2)}+¼+{fraction (0/8)}+{fraction (1/15)}) volts in the fourth procedure. The outputs COMP at the third and fourth procedures are “0” and “1”, respectively, which are sent to the successive approximation register
3
and stored therein.
The signal TZ from the A/D clock generating block
12
is explained below.
FIG. 40
shows a block diagram of an A/D clock generating block
12
. A clock signal CK, which is the source clock signal of the A/D converter, is frequency divided by a frequency divider
101
to supply a clock signal CK′ to an A/D control signal generating circuit
102
. The A/D control signal generating circuit
102
, which is controlled by the signal CK′, generates a control signal TZ to supply to the successive approximation register
3
.
FIG. 32
shows an example the frequency dividing circuit
101
. The ENABLE signal in the figure is a signal to actuate the A/D converter. When this signal becomes “H”, the A/D converter begins its operation. The frequency dividing circuit
101
generates the control signal CK′, by dividing the clock signal CK, and sends it to the A/D control signal generating circuit
102
. The A/D control signal generating circuit
102
is provided with two sets of latch A
103
and latch C
104
, as shown in FIG.
33
.
FIG.
34
and
FIG. 35
show an example of the circuit of the latch A
103
and the latch C
104
, respectively, which generate the signal TZ.
FIG. 41
is a timing chart of signals in the A/D clock generating block
12
, showing how the signal TZ is generated.
While the ENABLE signal is

Affiliated with

Also associated with

Rating

Method for controlling an analog/digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling an analog/digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling an analog/digital converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2526912