Method for controlling a sequence of accesses of a processor to

Details Method for controlling a sequence of accesses of a processor to Method for controlling a sequence of accesses of a processor to

1995-07-28

1998-05-19

Swann, Tod R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395431, 395454, 395481, 395494, 36518901, 36518905, 36523004, 36523001, G06F 1202

Patent

active

057548153

ABSTRACT:
The method controls the sequence (Q) of accesses (Z) of a processor (MP) to an allocated memory (SP) that is formed by at least two individually addressable, static sub-memories or, respectively, memory banks (SRAM 0, 1). Using a drive logic (ASL) inserted between the processor (MP) and, for example, two sub-memories (SRAM 0, 1), a first memory address (sa1) is switched in conformity with an access cycle to the addressed sub-memory (SRAM 0, 1) in a first access (Z) of a sequence (Q), a memory link address (sfa1) for the further sub-memories (SRAM 0, 1) is formed, is switched thereto and a reading or writing of a data (d) is initiated based on the criterion of the status information (sti). Subsequently, the sub-memories (SRAM 0, 1) are cyclically successively driven, a respective data (d) is read or stored using an intermediate memory (ZSP) and a memory link address (sfa2, 3) is respectively formed such that the two sub-memories (SRAM 0, 1) are successively and cyclically driven. As a result of the method, an especially advantageous memory design for communication systems (KS), particularly for telecommunication private branch exchanges, is realized with static sub-memories (SRAM 0, 1), whereby the memory accesses (Z) of a sequence (Q) of accesses (Z) occur at maximum processor access speed.

REFERENCES:
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5537577 (1996-07-01), Sugimura et al.
PC-Hardwarebuch, Hans-Peter Messmer, Addison-Wesley Publishing Company, (1992) pp. 290-298.
Microprocessor and Peripheral Handbook, vol. 1, Microprocessor, Intel the Microcomputer Company, (1988), pp. 4-1, 4-68 and 4-69.

Affiliated with

Also associated with

Rating

Method for controlling a sequence of accesses of a processor to does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling a sequence of accesses of a processor to , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling a sequence of accesses of a processor to will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1863675