Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-08
2002-09-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260, C365S185330
Reexamination Certificate
active
06456534
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory erase operation controller and to a method for controlling a flash memory erase operation, and more particularly it relates to a high-speed flash memory that eliminates malfunctioning by reliably discharging a residual charge remaining in a memory cell in a short period of time.
2. Related Art
Flash memories have been known in the past, and a method of erasing a flash memory of the past, such as the substrate erase method, is shown in the equivalent circuit diagram and structural cross-sectional view of FIG.
14
and FIG.
15
.
Specifically, in this substrate erase method, the gate voltage Vg is set to a negative voltage Vneg (for example, −8 V), the source voltage Vs and drain voltage Vd being left in the open state, and the substrate voltage Vb being set to a positive voltage Ves (for example, −8 V), so that floating electrons accumulated on the floating gate
158
are discharged to the substrate, thereby achieving erasure.
This memory cell is formed by a forming an N well
152
on a P-type substrate
151
and forming a P well
153
electrically isolated from the P-type substrate
151
, forming an N-type diffusion layer
154
on the N well
152
for the purpose of applying a voltage to the N well
152
, and forming a P-type well diffusion layer
155
on the P well
153
for the purpose of applying a voltage to the P well
153
.
Additionally, in this memory cell an n-type source diffusion layer
156
and an N-type drain diffusion layer
157
are formed on the P well
153
, and a floating gate
158
and control gate
159
are formed.
Each of the diffusion layers
156
and
157
are separated by a field insulation film
160
.
By adopting the above-noted structure, it is possible to use the substrate erase method, in which a positive voltage is applied to a substrate part of the memory cell.
FIG. 9
is a block diagram showing an example of the structure in a flash memory of using the above-described substrate erase memory, and in the operation of this device, a gate of the memory cell MC
1
is controlled by a row decoder
1
via a row line WL, and when erasing is to be performed, an output voltage Vneg of a negative voltage boosting circuit
2
is supplied to the gate of the memory cell via the row decoder
1
.
At times other than when an erase operation is performed, an N-type MOSFET MN
6
is provided at the connection node with the negative voltage Vneg for the purpose of setting a voltage of Vneg, which is the output of the negative voltage boosting circuit
2
, to the ground potential.
The drain CBL of the memory cell MC
1
is connected to the read /write circuit
3
, the source CSL of the memory cell is set to the ground potential GND by setting the N-type MOSFET MN
2
to the conducting state at the time of reading or writing, and the source CSL of the memory cell is placed in the open state by setting the N-type MOSFET MN
2
. to the non-conducting state when an erase is performed.
Additionally, the substrate CWL of the memory cell MC
1
is set to the ground potential GND by setting the N-type MOSFET MN
4
to the conducting state at the time of reading or writing, and the substrate CWL of the memory cell is supplied with the output Ves of the positive voltage boosting circuit
4
when an erase is performed.
The N-type MOSFETs MN
3
, MN
5
, MN
1
, and MN
7
are provided for the purpose of discharging the electrical charge on each one of the source CSL of the memory cell MC
1
, the substrate CWL, a drain CBL, and the gate WL.
As noted above, the erase operation for each memory cell MC
1
of this flash memory is performed in unites of sectors, and because the capacity of the memory cells is large (512 Kbits), the parasitic capacitance is extremely large, so that to prevent a large amount of noise being generated at the ground potential GND when a sudden discharging is done, the N-type MOSFETs MN
3
, MN
5
, MN
1
, and MN
7
are disposed so as to adjust the transistor capacity.
The erase operation in this flash memory is described. below, with references being made to the voltage waveform diagrams of FIG.
10
and FIG.
11
.
FIG. 10
is a voltage waveform diagram showing the operation at the start of an erase operation.
At time T
1
, the signals CSG, CWG, CWP, and XDP all change from the high level to the low level, resulting in setting the N-type MOSFETs MN
2
, MN
4
, and MN
6
to the non-conducting state and setting the P-type MOSFET MP
1
to the conducting state.
After time T
1
, by the start of the operation of the positive voltage boosting circuit and the negative voltage boosting circuit the positive erase voltage Ves rises from Vcc up to, for example, 8 V, and the negative erase voltage Vneg rises from the ground potential GND to, for example, −8 V, whereupon the memory cell is subjected to an erase operation by the gate WL also changing to −8 V.
When this occurs, CSL and CBL, which are the source and drain of the memory cell, are in the open state, with the PN junctions between the substrate of the memory cell and the source and the drain forward biased, so that current flow into the source and drain from the substrate, the resulting voltage being approximately 7.4 V, which is approximately 0.6 V lower than the forward breakdown voltage of the PN junction.
FIG. 11
is a voltage waveform diagram showing the end of the erase operation.
Specifically, at time T
3
the signal CWP changes from the low level to 8 V, which is the same as the Ves, so that the P-type MOSFET MP
1
changes to the non-conducting state, thereby cutting off the current path between the positive erase voltage Ves and the substrate CWL of the memory cell.
The negative voltage boosting circuit stops operating at the time T
3
.
Simultaneously with the above, the signals DISP and DISN change from the low level to the high, level, resulting in the N-type MOSFETs MN
1
, MN
3
, MN
5
, and MN
7
all going into the conducting state, which causes the negative voltage and positive voltage applied when erasing to discharge to the ground potential GND, and at time T
4
, at the time when the discharging has been completed, the operation of the positive voltage boosting circuit also stops, so that the positive erase voltage Ves stops the erase operation at Vcc.
In a flash memory of the past as described above, because the discharging of the various connection nodes (gate, source, drain, and substrate) of the memory cell at the completion of the erase operation is controlled separately, for example, it is extremely difficult to adjust the transistor capacity for each discharging, and various types of noise is generated.
For example,
FIG. 12
shows an example in which the discharging capacity of the N-type MOSFETs MN
7
to discharge the negative erase voltage Vneg is larger than that of the N-type MOSFETs MN
1
, MN
3
, and MN
5
.
The negative erase voltage Vneg transitions rapidly from −8 V to the ground potential GND at the time T
3
, this causing a shift of the ground potential GND within the memory cell in the negative voltage direction, leading to the possible blocking of the operation of the peripheral circuitry, and also because the negative erase voltage Vneg is capacitively coupled to the source, the substrate, and the drain of the memory cell via the gate capacitance of the memory cell, the potentials of the source, substrate, and drain of the memory cell are pulled upward, so that excessive stress is placed on the transistors connected to these nodes.
FIG. 13
shows an example in which the discharging capacities of the N-type MOSFETs MN
1
, MN
3
, and MN
5
which discharge the positive high-voltage terminal are greater than that of the N-type MOSFET MN
7
, which discharges the negative erase voltage Vneg.
The substrate CWL, source CSL, and drain CBL which are at a high positive voltage suddenly transition from 8 V to the ground potential GND at the time T
3
, causing the ground potential GND within the semiconductor memory to change in the positive voltage direction, leading to
Le Thong
NEC Corporation
Nelms David
LandOfFree
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