Method for controlled synchronization to an astable clock...

Details Method for controlled synchronization to an astable clock... Method for controlled synchronization to an astable clock...

2006-07-25

2006-07-25

Deppe, Betsy L. (Department: 2637)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C713S503000

Reexamination Certificate

active

07082175

ABSTRACT:
A method for controlled synchronization to an astable clock system, and reception unit corresponding thereto are disclosed. Soft synchronization using a slight change in the period duration of the clock signal produced makes it possible to alter said clock signal such that a phase difference between the stable clock signal produced by a phased locked loop upon a synchronization signal and the clock signal produced for an application is slowly reduced until the two clock signals are in synchronization with one another after a period of time.

REFERENCES:
patent: 4565975 (1986-01-01), Gegner et al.
patent: 4598257 (1986-07-01), Southard
patent: 5003559 (1991-03-01), Kanai et al.
patent: 5748569 (1998-05-01), Teodorescu et al.
patent: 6154508 (2000-11-01), Ott
patent: 6230021 (2001-05-01), Ohdachi
patent: 6297849 (2001-10-01), Stessen et al.
patent: 19932635 (2000-08-01), None
patent: 0652642 (1994-10-01), None

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