Method for control of random test vector generation

Details Method for control of random test vector generation Method for control of random test vector generation

1994-11-28

1997-01-14

Ramirez, Ellis B.

Excavating

371 511, 371 251, 364578, 395920, 39518301, G06F 1100

Patent

active

055947417

ABSTRACT:
A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.

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