Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-03-23
2001-02-13
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S002000
Reexamination Certificate
active
06188974
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a novel method for creating reduced-order models of various types of physical systems describable as linear circuit models with time delays.
INTRODUCTION OF THE INVENTION
Our motivation and methodology for the present invention are informed by an illustrative situation which centers on models for VLSI interconnects. High density circuit layouts and decreasing clock cycle times have amplified the effects of interconnect time delays and electromagnetic coupling in packaged electronic circuits, exacerbating the possibilities for signal delays and distortion. Simulation software for analyzing the performance of circuit packages requires reduced-order models of well-chosen subsets of the circuits in the package. PEEC models for the VLSI interconnects in the package are formulated as linear circuit models with time delays and comprise one large subset which requires model reduction.
SUMMARY OF THE INVENTION
With respect to the aforementioned package simulation models, it is necessary to create reduced-order models of the VLSI interconnects.
In high density layouts with very fast clock cycle times, models for VLSI interconnects must include the effects of the wire travel time and of the electromagnetic coupling between wires. Partial Element Equivalent Circuit (PEEC) models which are based upon integral formulations of Maxwell's equations and which are expressed as equivalent circuit formulations consist of linear systems of ordinary differential equations with multiple time delays. These delays occur in both state variables and derivatives of state variables. Tools are needed for systematic model reduction of these types of models.
We point out, by way of contrast and apposition, that the prior art has not adequately addressed this problem, and does not articulate a systematic method for generating reduced-order models of VLSI interconnects which include the effects of electromagnetic coupling and wire lengths. That is, to an extent the prior art may somehow intersect with the situation outlined above, it must inherently respond to it by recourse to unsatisfactory ad hoc or heuristic expedients.
We have now discovered a novel method for creating reduced-order models of PEEC models for VLSI interconnects. This method is equally applicable to other physical systems describable by time-invariant, linear systems of ordinary delay-differential equations. In this way, we advantageously solve the problem presented above, and fulfill an important need.
The method comprises the steps of:
a) representing an original physical system comprising time delays as an original linear circuit model;
b) transforming the original linear circuit model into a corresponding original transform domain circuit model;
c) locally approximating the original transform domain circuit model by a system without time delays, thereby generating at least one localized representation of the original system;
d) applying an iterative method to each localized representation of the original system, for identifying local characteristics of the original system; and
e) combining the identified local characteristics to obtain a reduced-order model for the original system.
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Cullum Jane Grace Kehoe
Ruehli Albert Emil
International Business Machines - Corporation
Kaufman, Esq. Stephen C.
McGinn & Gibb, P.C.
Teska Kevin J.
Thomson William
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