Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1995-07-13
2002-10-01
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S295000, C361S301400, C361S305000, C438S003000, C438S393000, C438S396000
Reexamination Certificate
active
06459137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to an improved method for constructing a ferroelectric capacitor on an integrated circuit substrate such as SiO
2
.
BACKGROUND OF THE INVENTION
Capacitors with ferroelectric dielectrics provide much larger capacitances per unit area of surface than do capacitors generated with other materials. In addition, these structures may be used to store data by utilizing the remnant polarization in certain types of ferroelectric materials.
A ferroelectric capacitor is constructed by sandwiching a layer of ferroelectric material such as lead lanthanum zirconate titantate (PLZT) between two electrodes. To construct this type of structure on an integrated circuit substrate, a bottom electrode is deposited on the substrate. A layer of ferroelectric material is then deposited on the bottom electrode. In the case of PLZT materials, the PLZT material is then sintered at 650° C. to form the desired perovskite structure in the material. The top electrode is then deposited on the ferroelectric layer. The structure is then covered with an insulating layer such as SiO
2
. Finally, connections are made to the bottom and top electrodes by opening via holes through the insulating layer.
Platinum is an excellent bottom electrode material to use with ferroelectric PZT and PLZT materials. First, platinum provides a low energy crystallization surface catalyzing the formation of a perovskite structure. Second, platinum maintains its electrical properties at the crystallization temperatures routinely used for sintering ferroelectric materials. And, finally, ferroelectric materials, especially PZT and PLZT, are found experimentally to demonstrate excellent ferroelectric properties with platinum bottom electrodes.
There are, however, several major problems with platinum bottom electrodes when used in connection with integrated circuits. First, platinum does not adhere very well to silicon dioxide or silicon nitride during the high temperature sintering (650° C.) of ferroelectric materials. The high degree of stress on the platinum SiO
2
bond generated by the ferroelectric film as it crystallizes peels the bottom electrode off the substrate. Platinum is not used with pure silicon because the silicon diffuses into the platinum, and subsequently the PLZT film. The silicon contaminates the PLZT film in a manner that alters the properties of the resulting capacitor.
To avoid these problems, prior art systems use a layer of another material, referred to as a “glue” layer, to bond the platinum to the silicon dioxide or silicon nitride, The glue layer also prevents diffusion of the silicon into the platinum and PLZT layers. The preferred glue material is metallic titanium. This is the only material that is consistently successful at this role. The bottom electrode is typically deposited by first depositing a layer of titanium directly on a silicon dioxide or silicon nitride covered substrate and then depositing a layer of platinum on the metallic titanium.
While the titanium glue layer solves the problem of bonding the bottom electrode to the substrate, it introduces other problems when the platinum layer is to be used as a bottom electrode for a PLZT capacitor. The titanium glue layer diffuses into the platinum during the sintering stage of the ferroelectric film. The titanium in the platinum oxidizes as it diffuses into the platinum. This makes the bottom electrode into a sandwich of platinum layers with an insulating TiO
2
layer in between. Additionally, the titanium oxide occupies more space than either the platinum or titanium alone. This expands the volume of the bottom electrode and creates additional stress in the resulting capacitor. Finally, some of the titanium may reach the ferroelectric material and diffuse into the ferroelectric. In the case of PZT or PLZT, of which titanium is a major constituent, this can change the composition of the ferroelectric material near the surface of the bottom electrode, and hence, lead to changes in the ferroelectric properties.
In addition to altering the electrical properties of the capacitor, the diffused titanium makes it difficult to pattern the bottom electrode. Neither titanium dioxide, nor the titanium/platinum alloy formed in the platinum, are easily etched in the patterning steps. Even ion milling has difficulty etching these combinations. Consequently, as soon as the ferroelectric material has been sintered and the titanium has diffused into the platinum bottom electrode, the bottom electrode becomes unetchable for integrated circuit manufacturing purposes.
To avoid the problems resulting from titanium diffusing through the platinum to the ferroelectric layer, care must be taken to use just enough titanium in thickness to bond the bottom electrode to the substrate during sintering while using sufficient platinum to guarantee that any titanium that diffuses into the platinum will not reach the platinum/ferroelectric boundary. For example, it has been found experimentally that 1000 Å of titanium and 2500 Å of platinum provide sufficient bonding while not degrading the performance of the capacitor beyond acceptable limits.
Unfortunately, the thicker platinum layer required to alleviate the titanium diffusion problem interferes with the integrated circuit process. Platinum is very difficult to etch. Consequently, it has a tendency to undercut strongly. To compensate for this undercut, large etch biases must be used during fabrication. For example, to obtain a 6&mgr; bottom electrode line using a 2500 Å thick platinum layer, one must start with 10&mgr; wide lines on the etch mask to compensate for up to 2&mgr; of overetch from both directions. To accommodate this initial. line width, the devices being fabricated must be spaced further apart. The resulting spacing of devices makes it impossible to generate capacitors at densities consistent with the DRAM structures currently being fabricated. In addition, the etch step is difficult to control over large areas; hence poor uniformity and yield across the wafer result. To obtain satisfactory results, the platinum layer must be made 1000 A or less in thickness. However, this thickness is insufficient to alleviate the titanium diffusion problems discussed above.
Another problem introduced by the thick platinum layer used in prior art devices relates to the artifacts introduced by the thickness of the bottom electrode. Consider an integrated circuit having a capacitor constructed thereon. Connections must be made between the circuit elements and the top and bottom electrodes of the capacitor. The interconnect lines must travel up the side of the capacitor. The height of the capacitor has a significant effect on metalization yield. The 3500 A required by the prior art bottom electrode adds significantly to the capacitor height, and hence, significantly reduces device yields.
Broadly, it is the object of the present invention to provide an improved ferroelectric capacitor structure and method for constructing the same.
It is a further object of the present invention to provide a ferroelectric capacitor structure in which the bottom electrode is significantly thinner than prior art bottom electrodes.
It is a still further object of the present invention to provide a ferroelectric capacitor structure having a reduced height relative to prior art ferroelectric capacitor structures.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention comprises an improved ferroelectric capacitor structure and a method for constructing the same on a silicon substrate. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide is preferably generated by depositing a layer of metallic titanium and
Bullington Jeff Allen
Evans, Jr. Joseph Tate
Montross, Jr. Carl Elijah
Eckert II George C.
Radiant Technologies, Inc
Ward Calvin B.
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