Patent
1997-08-05
2000-03-07
Teska, Kevin J.
39550023, G06F 1900
Patent
active
060351144
ABSTRACT:
The present invention discloses a method for constructing the fault classification tables of analog circuits, and the fault classification tables can be further applied to construct analog CAT tools. The constructing method uses the fault models but the normal models inserting in parts of the analog circuit components, and then utilizes a circuit simulator to obtain waveform from the defect analog circuit. Exclusive and non-exclusive classification schemes are applied to establish the failure modes of the defect analog circuit when the waveform is recorded as a fault dictionary. It is unnecessary to construct a real analog circuit as the conventional does.
REFERENCES:
patent: 5099436 (1992-03-01), McCown et al.
patent: 5511162 (1996-04-01), Hamada et al.
patent: 5515384 (1996-05-01), Horton, III
patent: 5544308 (1996-08-01), Giordano et al.
Sujoj Sen et al. "Simulation-Based Testability Analysis and Fault Diagnosis", IEEE, Sep. 1999.
Chan Yi-Fan
Chang Shou-Chieh
Mao Wei-Lung
Tsao Ying-Kun
Tseng I-Shih
Choi Kyle J.
Institute for Information Industry
Teska Kevin J.
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