Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1982-02-10
1985-05-14
Hearn, Brian E.
Metal working
Method of mechanical manufacture
Assembling or joining
9577C, 148 15, 357 236, 357 2314, H01L 2978
Patent
active
045163120
ABSTRACT:
A method for constructing delay circuits in a master slice IC formed on a semiconductor substrate. The master slice IC comprises regularly arranged MIS transistors having gate electrodes. The MIS transistors includes various logic circuits. A delay circuit is formed between two logic circuits. The delay circuit comprises a resistor and a capacitor. The resistor is constructed using the resistances of the gate electrodes by sequentially connecting the gate electrodes between two logic circuits. The capacitor is constructed using capacitances formed between the gate electrodes and the semiconductor substrate. A precise delay time of a delay circuit having a small area can be obtained.
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IEEE Transactions on Circuits and Systems, vol. CAS-28, No. 8, Aug. 1981, New York, S. M. Kang, "A Design of CMOS Polycells for LSI Circuits", pp. 838-843.
Fujitsu Limited
Hearn Brian E.
Hey David A.
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