Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-03-23
2002-08-27
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C438S612000
Reexamination Certificate
active
06440771
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits, and more particularly, to an interposer assembly apparatus and method.
BACKGROUND OF THE INVENTION
The three stages of semiconductor device manufacture are wafer fabrication, assembly and testing. The testing stage always includes an evaluation of the electrical connections within the device, and often includes bum-in testing as well. In a conventional manufacturing process, before testing is done, the wafer is diced into individual dies, and the dies are assembled into packages. The purpose of the package is to protect the die as well as provide connections that allow the package to be attached to a testing apparatus or printed circuit board. The fact that the testing of the individual dies does not take place until the dies have been packaged increases the cost. This increased cost stems from the greater complexity, size, and quantity of the testing apparatus, as well as the difficulty of manipulating large quantities of separately packaged dies.
In addition to the tooling and labor costs associated with electrical and bum-in testing of individually packaged dies, there is also the wasted expense of packaging the dies that will subsequently be found to be defective. Since in a conventional process all dies must be packaged before any testing can be done, this means that all defective die will necessarily be packaged, and the expense of doing so is complete waste. For example, if 6%, a conservative estimate, of the dies fail either the electrical or burn-in testing, that is 60 die packaging operations that are wasted for every 1000 dies that are produced. The ability to test the dies before the packaging operations would obviously reduce production costs.
The savings associated with a wafer level testing protocol are multifold. In addition to the savings associated with the elimination of unnecessary packaging operations, inventory carrying costs are reduced because the processing cycle times are reduced since “good” dies are identified earlier in the manufacturing process. An additional benefit can be obtained if the substrate can serve as packaging for the die. The elimination of the requirement for additional packaging after test and burn-in greatly reduces not only direct product costs, but cycle time costs as well.
Two problems exist when attaching a substrate to a wafer to form a wafer interposer. The first is variances in planarity between the substrate and the wafer. Any planar variances require further variances in the height of the solder connections used to attach the two surfaces. Since the solder connections will have height variances, they must be able to absorb enough compression force to make all the contacts. The second problem is the difference between the two surfaces in thermal expansion. Temperature excursions cause one material to expand at a different rate than the other. This causes a shear force to be exerted against the solder connecting the wafer and substrate. Underfill can help reduce this shear force. However, if the thermal expansion differences are great enough, not even underfill will prevent the solder connections from breaking and losing connection.
Accordingly, there is a need for an interposer connection technique that meets all of the criteria outlined above, allows testing at the wafer level before dicing, and eliminates the need for temporarily packaging the die in a carrier, as well as providing packing for the semiconductor die.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for testing wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs.
The interposer assembly of the present invention revolutionizes the semiconductor fabrication process by enabling burn-in and parametric testing at the wafer level. The interposer eliminates the need to singulate, package, test, and unpackage each die in order to arrive at the Known Good Die product stage. The interposer remains attached to the die following dicing, and thus provides the additional benefit of redistributing the die I/O pads so that they can be larger and more easily accessed and/or mated to other downstream components.
One form of the present invention provides a technique for constructing an interposer using conductive columns to form an interconnection between a substrate and a wafer. Conductive columns are capable of absorbing height compression as well as shear forces to a much greater extent than a typical conductive bump. The conductive columns can be formed using a variety of techniques.
Another form of the present invention provides an interposer assembly comprising a substrate, a wafer, connecting material and no-flow underfill. The substrate and the wafer each have an upper and a lower surface. The upper and lower surfaces of the substrate have one or more electrical contacts. The upper surface of the wafer further comprises one or more die, each die having electrical contacts. The electrical contacts of the upper surface of the substrate are connected to the electrical contacts of the lower surface of the substrate through electrical pathways. Connecting material in the form of conductive columns, subsequently surrounded by no-flow underfill, physically connects the electrical contacts of the lower surface of the substrate to the electrical contacts of the die, providing a total connection path from the die to the electrical contacts on the upper surface of the substrate.
REFERENCES:
patent: 6133070 (2000-10-01), Yagi et al.
patent: 6319829 (2001-11-01), Pasco et al.
Danamraj & Youst P.C.
Eaglestone Partners I, LLC
Nguyen Tuan H.
Youst Lawrence R.
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