Method for constructing a reduced capacitance chip carrier

Details Method for constructing a reduced capacitance chip carrier Method for constructing a reduced capacitance chip carrier

1992-04-08

1994-11-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437217, 437220, 297786, H01L 2152, H01L 2156, H01L 2158, H01L 2160

Patent

active

053690591

ABSTRACT:
A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.

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Microelectronics Packaging Handbook, Van Nostrand Reinhold, 1989, pp. 749-750, TK7874,T824.

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