Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2011-01-18
2011-01-18
Geyer, Scott B (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C716S030000, C716S030000
Reexamination Certificate
active
07871831
ABSTRACT:
An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad. The outer portion of the flip chip is traversed, and the second projection is generated based on the order in which I/O pad representations are encountered. Connections between bump and I/O representations are made and connecting between bumps and I/O pads determined based on the connections between bump and I/O pad representations of respective first and second projections. The determined connections can be adjusted according to a hierarchy of bump representations to reduce or eliminate congestion, e.g., by changing a sequence of or deleting bump representations.
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Cho Jaejoo
Tu Phil
Yao Tao
Cadence Design Systems Inc.
Geyer Scott B
Sene Pape
Vista IP Law Group LLP
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