Method for configuring an FPGA for large FFTs and other vector r

Details Method for configuring an FPGA for large FFTs and other vector r Method for configuring an FPGA for large FFTs and other vector r

1997-03-14

1999-11-23

Ngo, Ohuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708440, G06F 752, G06F 738

Patent

active

059917881

ABSTRACT:
A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

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Cooley, James W. and Tukey, John W., Apr. 1965, "An Algorithm for the Machine Calculation of Complex Fourier Series," Math of Comput., vol. 19, pp. 297-301.
New, Bernie, Aug. 17, 1995, "A Distributed Arithmetic Approach to Designing Scalable DSP Chips," EDN, pp. 107-114.
White, Stanley A., Jul. 1989, "Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review," IEEE ASSP Magazine, pp. 4-19.

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