Method for compiling loops containing prefetch instructions that

Details Method for compiling loops containing prefetch instructions that Method for compiling loops containing prefetch instructions that

1996-07-05

1999-09-07

Maung, Zarni

395705, G06F 945

Patent

active

059500077

ABSTRACT:
Prefetch instructions having a function to move data to a cache memory from main memory are scheduled simultaneously with execution of other instructions. The prefetch instructions are scheduled by replacing, with the original prefetch instructions, the virtual prefetch instructions obtained by unrolling a kernel section of the schedule constituted by generating a dependency graph having dependent relationships between the prefetch instruction and the memory reference instruction, and then applying the software pipelining thereto, or by further unrolling the kernel section of the constituted schedule to delete the redundant prefetch instructions, or further by applying the software pipelining to the dependency graph which is formed by combining a plurality of prefetch instructions and replacing the prefetch instructions with virtual prefetch instructions.

REFERENCES:
patent: 5303357 (1994-04-01), Inoue et al.
patent: 5367651 (1994-11-01), Smith et al.
patent: 5491823 (1996-02-01), Ruttenberg
patent: 5557761 (1996-09-01), Chan et al.
patent: 5664193 (1997-09-01), Tirumalai
patent: 5704053 (1997-12-01), Santhanam
patent: 5752037 (1998-05-01), Gornish et al.
patent: 5761515 (1998-06-01), Barton, III et al.
patent: 5794029 (1998-08-01), Babaian et al.
patent: 5797013 (1998-08-01), Mahadevan et al.
patent: 5809308 (1998-09-01), Tirumalai
patent: 5819088 (1998-10-01), Reinders
patent: 5835776 (1998-11-01), Tirumalai et al.
S. Ramakrishnan, "Software Pipelining in PA-RISC Compilers," Hewlett-Packard Journal, Jun. 1992, pp. 39-45.
T. Mowry et al, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proceedings of the Fifth International Conference on Architectural Support for Programming Language and Operating Systems, 1992, pp. 62-73.
D. Callahan et al, "Software Prefetching," 1991 ACM 0-89791-380, pp. 40-52.
G. Kurpanek et al, "PA7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface," Hewlett-Packard Company, 1994 IEEE, pp. 375-382.

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