Method for compiling computer instructions for increasing instru

Details Method for compiling computer instructions for increasing instru Method for compiling computer instructions for increasing instru

1990-03-27

1994-04-12

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642804, 364280, 3642805, 364243, 3642434, 36424341, 36424342, G06F 944

Patent

active

053033779

ABSTRACT:
Method for compiling program instructions to reduce instruction cache misses and instruction cache pollution. The program is analyzed for instructions which result in a non-sequential transfer of control in the program. The presence of branch instructions and program loops are identified and analyzed. The instructions are placed in lines, and the lines are placed in a sequence to minimize potential misses.

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A. D. Samples et al, "Code Reorganization for Instruction Caches," Report No. UCB/CSD 88/447, University of CA, Berkeley Oct. 1988.
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Fuhrt et al, "Compiler-Directed Cache Strategy for GaAs Microprocessor Architectures", 1988 IEEE Southeastern Conf. Proc., pp. 186-192.
McFarling "Program Optimization for Instruction Caches", ASPLOS Proceedings ACM x-303, pp. 183-191 1989.
H. Cheong, et al., "Compiler-Directed Cache Management in Multiprocessors", Computer, Jun. 1990, vol. 23, No. 6 pp. 39-47.
D. Gannon, "Strategies for Cache and Local Memory Management by Global Program Transformation", Super Computing, 1st Intern. Conf Proc, 1988, pp. 229-254.
Karlovsky, "Automatic Management of Programmable Caches: Algorithms and Experience", CSRD Rpt #892, Center for Supercomputing Research and Development, Jul. 1989.
Weber, "Compiler Optimization in RISC Systems", Digital-Technical Journal, vol. 2, No. 2, Spring 1990, pp. 89-95.

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