Method for compensating temperature in crystal oscillator

Details Method for compensating temperature in crystal oscillator Method for compensating temperature in crystal oscillator

2005-03-22

2005-03-22

Pascal, Robert (Department: 2817)

Oscillators

Electromechanical resonator

Crystal

C331S1160FE, C331S03600C

Reexamination Certificate

active

06870434

ABSTRACT:
The present invention relates to a method for compensating temperature in a crystal oscillator including a capacitor array consisted of a first bank of unit capacitors each with low capacitance and a second bank of unit capacitors each with high capacitance. The method comprising the steps of calculating memory address that stores information about the capacitor array address in accordance with the temperature that is subtracted from present temperature by a temperature offset code; reading data from a memory address corresponding to remain bits excepted lowest bit when the lowest bit is 0 among the memory address; averaging data read from a memory address corresponding to remain bits excepted lowest bit and data of a memory address incremented by 1 from the memory address when the lowest bit is 1 among the memory address; transmitting data read from the memory address or averaged data to the first bank or second bank by comparing the memory address and temperature boundary code; and adjusting the capacitor array with capacitance corresponding to a present temperature by using data transmitted to the first bank or second bank.

REFERENCES:
patent: 5777524 (1998-07-01), Wojewoda et al.
patent: 5994970 (1999-11-01), Cole et al.
patent: 20020180544 (2002-12-01), Fukayama et al.
patent: 07-221547 (1995-08-01), None
patent: 2001-09709 (2001-02-01), None
patent: 010009126 (2001-05-01), None
Ralf Achenbach, et al.; “A Digitally Temperature-Compensated Crystal Oscillator”; IEEE Journal of Solid-State Circuits; vol. 5, No. 4; Dec. 1997; pp. 1502-1506.
Oiuting Huang, et al.; “Design Considerations for High-Frequency Crystal Oscillators Digitally Trimmable to Sub-ppm Accuracy”; IEEE Transaction on Very Large Scale Integration (VLSI) Systems; vol. 5, No. 4; Dec. 1997; pp. 408-416.

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